300   Arm64ManagedRegister dst = m_dst.AsArm64();  in LoadRef()  local
301   CHECK(dst.IsXRegister()) << dst;  in LoadRef()
302   LoadWFromOffset(kLoadWord, dst.AsOverlappingWRegister(), SP, offs.Int32Value());  in LoadRef()
309   Arm64ManagedRegister dst = m_dst.AsArm64();  in LoadRef()  local
311   CHECK(dst.IsXRegister() && base.IsXRegister());  in LoadRef()
312   LoadWFromOffset(kLoadWord, dst.AsOverlappingWRegister(), base.AsXRegister(),  in LoadRef()
315     WRegister ref_reg = dst.AsOverlappingWRegister();  in LoadRef()
323   Arm64ManagedRegister dst = m_dst.AsArm64();  in LoadRawPtr()  local
325   CHECK(dst.IsXRegister() && base.IsXRegister());  in LoadRawPtr()
328   temps.Exclude(reg_x(dst.AsXRegister()), reg_x(base.AsXRegister()));  in LoadRawPtr()
329   ___ Ldr(reg_x(dst.AsXRegister()), MEM_OP(reg_x(base.AsXRegister()), offs.Int32Value()));  in LoadRawPtr()
333   Arm64ManagedRegister dst = m_dst.AsArm64();  in LoadRawPtrFromThread()  local
334   CHECK(dst.IsXRegister()) << dst;  in LoadRawPtrFromThread()
335   LoadFromOffset(dst.AsXRegister(), TR, offs.Int32Value());  in LoadRawPtrFromThread()
340   Arm64ManagedRegister dst = m_dst.AsArm64();  in Move()  local
342   if (!dst.Equals(src)) {  in Move()
343     if (dst.IsXRegister()) {  in Move()
346         ___ Mov(reg_w(dst.AsOverlappingWRegister()), reg_w(src.AsWRegister()));  in Move()
349           ___ Mov(reg_x(dst.AsXRegister()), reg_x(src.AsXRegister()));  in Move()
351           ___ Mov(reg_x(dst.AsXRegister()), reg_x(src.AsOverlappingXRegister()));  in Move()
354     } else if (dst.IsWRegister()) {  in Move()
356       ___ Mov(reg_w(dst.AsWRegister()), reg_w(src.AsWRegister()));  in Move()
357     } else if (dst.IsSRegister()) {  in Move()
359       ___ Fmov(reg_s(dst.AsSRegister()), reg_s(src.AsSRegister()));  in Move()
361       CHECK(dst.IsDRegister()) << dst;  in Move()
363       ___ Fmov(reg_d(dst.AsDRegister()), reg_d(src.AsDRegister()));  in Move()