739   VOID    *PageTable;  in Gen4GPageTable()  local
769   PageTable = AllocatePageTableMemory (5 + PagesNeeded);  in Gen4GPageTable()
770   ASSERT (PageTable != NULL);  in Gen4GPageTable()
772   PageTable = (VOID *)((UINTN)PageTable);  in Gen4GPageTable()
773   Pte = (UINT64*)PageTable;  in Gen4GPageTable()
784 …Pte[Index] = (UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1) + (Is32BitPageTable ? IA32_PAE_PDPTE_A…  in Gen4GPageTable()
796     Pages = (UINTN)PageTable + EFI_PAGES_TO_SIZE (5);  in Gen4GPageTable()
798     Pdpte = (UINT64*)PageTable;  in Gen4GPageTable()
826   return (UINT32)(UINTN)PageTable;  in Gen4GPageTable()
839   IN      UINT64                    *PageTable,  in SetCacheability()  argument
853     ASSERT (PageTable[PTIndex] & IA32_PG_P);  in SetCacheability()
854     PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask);  in SetCacheability()
858   ASSERT (PageTable[PTIndex] & IA32_PG_P);  in SetCacheability()
859   PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask);  in SetCacheability()
867   if ((PageTable[PTIndex] & IA32_PG_PS) != 0) {  in SetCacheability()
877       NewPageTable[Index] = PageTable[PTIndex];  in SetCacheability()
885     PageTable[PTIndex] = ((UINTN)NewPageTableAddress & gPhyMask) | PAGE_ATTRIBUTE_BITS;  in SetCacheability()
888   ASSERT (PageTable[PTIndex] & IA32_PG_P);  in SetCacheability()
889   PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask);  in SetCacheability()
892   ASSERT (PageTable[PTIndex] & IA32_PG_P);  in SetCacheability()
893   PageTable[PTIndex] &= ~((UINT64)((IA32_PG_PAT_4K | IA32_PG_CD | IA32_PG_WT)));  in SetCacheability()
894   PageTable[PTIndex] |= (UINT64)Cacheability;  in SetCacheability()