1 /* 2 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __CORTEX_A53_H__ 8 #define __CORTEX_A53_H__ 9 10 /* Cortex-A53 midr for revision 0 */ 11 #define CORTEX_A53_MIDR U(0x410FD030) 12 13 /* Retention timer tick definitions */ 14 #define RETENTION_ENTRY_TICKS_2 U(0x1) 15 #define RETENTION_ENTRY_TICKS_8 U(0x2) 16 #define RETENTION_ENTRY_TICKS_32 U(0x3) 17 #define RETENTION_ENTRY_TICKS_64 U(0x4) 18 #define RETENTION_ENTRY_TICKS_128 U(0x5) 19 #define RETENTION_ENTRY_TICKS_256 U(0x6) 20 #define RETENTION_ENTRY_TICKS_512 U(0x7) 21 22 /******************************************************************************* 23 * CPU Extended Control register specific definitions. 24 ******************************************************************************/ 25 #define CORTEX_A53_ECTLR_EL1 S3_1_C15_C2_1 26 27 #define CORTEX_A53_ECTLR_SMP_BIT (U(1) << 6) 28 29 #define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0) 30 #define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT) 31 32 #define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3) 33 #define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT) 34 35 /******************************************************************************* 36 * CPU Memory Error Syndrome register specific definitions. 37 ******************************************************************************/ 38 #define CORTEX_A53_MERRSR_EL1 S3_1_C15_C2_2 39 40 /******************************************************************************* 41 * CPU Auxiliary Control register specific definitions. 42 ******************************************************************************/ 43 #define CORTEX_A53_CPUACTLR_EL1 S3_1_C15_C2_0 44 45 #define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT U(44) 46 #define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (U(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT) 47 #define CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT U(27) 48 #define CORTEX_A53_CPUACTLR_EL1_RADIS (U(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT) 49 #define CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT U(25) 50 #define CORTEX_A53_CPUACTLR_EL1_L1RADIS (U(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT) 51 #define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT U(24) 52 #define CORTEX_A53_CPUACTLR_EL1_DTAH (U(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT) 53 54 /******************************************************************************* 55 * L2 Auxiliary Control register specific definitions. 56 ******************************************************************************/ 57 #define CORTEX_A53_L2ACTLR_EL1 S3_1_C15_C0_0 58 59 #define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14) 60 #define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3) 61 /******************************************************************************* 62 * L2 Extended Control register specific definitions. 63 ******************************************************************************/ 64 #define CORTEX_A53_L2ECTLR_EL1 S3_1_C11_C0_3 65 66 #define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0) 67 #define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT) 68 69 /******************************************************************************* 70 * L2 Memory Error Syndrome register specific definitions. 71 ******************************************************************************/ 72 #define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3 73 74 #if !ERROR_DEPRECATED 75 /* 76 * These registers were previously wrongly named. Provide previous definitions 77 * so as not to break platforms that continue using them. 78 */ 79 #define CORTEX_A53_ACTLR_EL1 CORTEX_A53_CPUACTLR_EL1 80 81 #define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT 82 #define CORTEX_A53_ACTLR_ENDCCASCI CORTEX_A53_CPUACTLR_EL1_ENDCCASCI 83 #define CORTEX_A53_ACTLR_RADIS_SHIFT CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT 84 #define CORTEX_A53_ACTLR_RADIS CORTEX_A53_CPUACTLR_EL1_RADIS 85 #define CORTEX_A53_ACTLR_L1RADIS_SHIFT CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT 86 #define CORTEX_A53_ACTLR_L1RADIS CORTEX_A53_CPUACTLR_EL1_L1RADIS 87 #define CORTEX_A53_ACTLR_DTAH_SHIFT CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT 88 #define CORTEX_A53_ACTLR_DTAH CORTEX_A53_CPUACTLR_EL1_DTAH 89 #endif /* !ERROR_DEPRECATED */ 90 91 #endif /* __CORTEX_A53_H__ */ 92