1 /* 2 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __CORTEX_A57_H__ 8 #define __CORTEX_A57_H__ 9 #include <utils_def.h> 10 11 /* Cortex-A57 midr for revision 0 */ 12 #define CORTEX_A57_MIDR U(0x410FD070) 13 14 /* Retention timer tick definitions */ 15 #define RETENTION_ENTRY_TICKS_2 U(0x1) 16 #define RETENTION_ENTRY_TICKS_8 U(0x2) 17 #define RETENTION_ENTRY_TICKS_32 U(0x3) 18 #define RETENTION_ENTRY_TICKS_64 U(0x4) 19 #define RETENTION_ENTRY_TICKS_128 U(0x5) 20 #define RETENTION_ENTRY_TICKS_256 U(0x6) 21 #define RETENTION_ENTRY_TICKS_512 U(0x7) 22 23 /******************************************************************************* 24 * CPU Extended Control register specific definitions. 25 ******************************************************************************/ 26 #define CORTEX_A57_ECTLR_EL1 S3_1_C15_C2_1 27 28 #define CORTEX_A57_ECTLR_SMP_BIT (U(1) << 6) 29 #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (U(1) << 38) 30 #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (U(0x3) << 35) 31 #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (U(0x3) << 32) 32 33 #define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0) 34 #define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) 35 36 /******************************************************************************* 37 * CPU Memory Error Syndrome register specific definitions. 38 ******************************************************************************/ 39 #define CORTEX_A57_MERRSR_EL1 S3_1_C15_C2_2 40 41 /******************************************************************************* 42 * CPU Auxiliary Control register specific definitions. 43 ******************************************************************************/ 44 #define CORTEX_A57_CPUACTLR_EL1 S3_1_C15_C2_0 45 46 #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59) 47 #define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54) 48 #define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52) 49 #define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) 50 #define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) 51 #define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38) 52 #define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) 53 #define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27) 54 #define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25) 55 #define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) 56 57 /******************************************************************************* 58 * L2 Control register specific definitions. 59 ******************************************************************************/ 60 #define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2 61 62 #define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) 63 #define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) 64 65 #define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) 66 #define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) 67 68 #define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21) 69 70 /******************************************************************************* 71 * L2 Extended Control register specific definitions. 72 ******************************************************************************/ 73 #define CORTEX_A57_L2ECTLR_EL1 S3_1_C11_C0_3 74 75 #define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT U(0) 76 #define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (U(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) 77 78 /******************************************************************************* 79 * L2 Memory Error Syndrome register specific definitions. 80 ******************************************************************************/ 81 #define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3 82 83 #if !ERROR_DEPRECATED 84 /* 85 * These registers were previously wrongly named. Provide previous definitions so 86 * as not to break platforms that continue using them. 87 */ 88 #define CORTEX_A57_ACTLR_EL1 CORTEX_A57_CPUACTLR_EL1 89 90 #define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB 91 #define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE 92 #define CORTEX_A57_ACTLR_DIS_OVERREAD CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD 93 #define CORTEX_A57_ACTLR_NO_ALLOC_WBWA CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA 94 #define CORTEX_A57_ACTLR_DCC_AS_DCCI CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI 95 #define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH 96 #define CORTEX_A57_ACTLR_DIS_STREAMING CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING 97 #define CORTEX_A57_ACTLR_DIS_L1_STREAMING CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING 98 #define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR 99 #endif /* !ERROR_DEPRECATED */ 100 101 #endif /* __CORTEX_A57_H__ */ 102