1 /** @file 2 Platform TPM Profile Specification definition for TPM2.0. 3 It covers both FIFO and CRB interface. 4 5 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 6 This program and the accompanying materials 7 are licensed and made available under the terms and conditions of the BSD License 8 which accompanies this distribution. The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14 **/ 15 16 #ifndef _TPM_PTP_H_ 17 #define _TPM_PTP_H_ 18 19 // 20 // PTP FIFO definition 21 // 22 23 // 24 // Set structure alignment to 1-byte 25 // 26 #pragma pack (1) 27 28 // 29 // Register set map as specified in PTP specification Chapter 5 30 // 31 typedef struct { 32 /// 33 /// Used to gain ownership for this particular port. 34 /// 35 UINT8 Access; // 0 36 UINT8 Reserved1[7]; // 1 37 /// 38 /// Controls interrupts. 39 /// 40 UINT32 IntEnable; // 8 41 /// 42 /// SIRQ vector to be used by the TPM. 43 /// 44 UINT8 IntVector; // 0ch 45 UINT8 Reserved2[3]; // 0dh 46 /// 47 /// What caused interrupt. 48 /// 49 UINT32 IntSts; // 10h 50 /// 51 /// Shows which interrupts are supported by that particular TPM. 52 /// 53 UINT32 InterfaceCapability;// 14h 54 /// 55 /// Status Register. Provides status of the TPM. 56 /// 57 UINT8 Status; // 18h 58 /// 59 /// Number of consecutive writes that can be done to the TPM. 60 /// 61 UINT16 BurstCount; // 19h 62 /// 63 /// Additional Status Register. 64 /// 65 UINT8 StatusEx; // 1Bh 66 UINT8 Reserved3[8]; 67 /// 68 /// Read or write FIFO, depending on transaction. 69 /// 70 UINT32 DataFifo; // 24h 71 UINT8 Reserved4[8]; // 28h 72 /// 73 /// Used to identify the Interface types supported by the TPM. 74 /// 75 UINT32 InterfaceId; // 30h 76 UINT8 Reserved5[0x4c]; // 34h 77 /// 78 /// Extended ReadFIFO or WriteFIFO, depending on the current bus cycle (read or write) 79 /// 80 UINT32 XDataFifo; // 80h 81 UINT8 Reserved6[0xe7c]; // 84h 82 /// 83 /// Vendor ID 84 /// 85 UINT16 Vid; // 0f00h 86 /// 87 /// Device ID 88 /// 89 UINT16 Did; // 0f02h 90 /// 91 /// Revision ID 92 /// 93 UINT8 Rid; // 0f04h 94 UINT8 Reserved[0xfb]; // 0f05h 95 } PTP_FIFO_REGISTERS; 96 97 // 98 // Restore original structure alignment 99 // 100 #pragma pack () 101 102 // 103 // Define pointer types used to access TIS registers on PC 104 // 105 typedef PTP_FIFO_REGISTERS *PTP_FIFO_REGISTERS_PTR; 106 107 // 108 // Define bits of FIFO Interface Identifier Register 109 // 110 typedef union { 111 struct { 112 UINT32 InterfaceType:4; 113 UINT32 InterfaceVersion:4; 114 UINT32 CapLocality:1; 115 UINT32 Reserved1:2; 116 UINT32 CapDataXferSizeSupport:2; 117 UINT32 CapFIFO:1; 118 UINT32 CapCRB:1; 119 UINT32 CapIFRes:2; 120 UINT32 InterfaceSelector:2; 121 UINT32 IntfSelLock:1; 122 UINT32 Reserved2:4; 123 UINT32 Reserved3:8; 124 } Bits; 125 UINT32 Uint32; 126 } PTP_FIFO_INTERFACE_IDENTIFIER; 127 128 // 129 // Define bits of FIFO Interface Capability Register 130 // 131 typedef union { 132 struct { 133 UINT32 DataAvailIntSupport:1; 134 UINT32 StsValidIntSupport:1; 135 UINT32 LocalityChangeIntSupport:1; 136 UINT32 InterruptLevelHigh:1; 137 UINT32 InterruptLevelLow:1; 138 UINT32 InterruptEdgeRising:1; 139 UINT32 InterruptEdgeFalling:1; 140 UINT32 CommandReadyIntSupport:1; 141 UINT32 BurstCountStatic:1; 142 UINT32 DataTransferSizeSupport:2; 143 UINT32 Reserved:17; 144 UINT32 InterfaceVersion:3; 145 UINT32 Reserved2:1; 146 } Bits; 147 UINT32 Uint32; 148 } PTP_FIFO_INTERFACE_CAPABILITY; 149 150 /// 151 /// InterfaceVersion 152 /// 153 #define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_12 0x0 154 #define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_13 0x2 155 #define INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP 0x3 156 157 158 // 159 // Define bits of ACCESS and STATUS registers 160 // 161 162 /// 163 /// This bit is a 1 to indicate that the other bits in this register are valid. 164 /// 165 #define PTP_FIFO_VALID BIT7 166 /// 167 /// Indicate that this locality is active. 168 /// 169 #define PTP_FIFO_ACC_ACTIVE BIT5 170 /// 171 /// Set to 1 to indicate that this locality had the TPM taken away while 172 /// this locality had the TIS_PC_ACC_ACTIVE bit set. 173 /// 174 #define PTP_FIFO_ACC_SEIZED BIT4 175 /// 176 /// Set to 1 to indicate that TPM MUST reset the 177 /// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the 178 /// locality that is writing this bit. 179 /// 180 #define PTP_FIFO_ACC_SEIZE BIT3 181 /// 182 /// When this bit is 1, another locality is requesting usage of the TPM. 183 /// 184 #define PTP_FIFO_ACC_PENDIND BIT2 185 /// 186 /// Set to 1 to indicate that this locality is requesting to use TPM. 187 /// 188 #define PTP_FIFO_ACC_RQUUSE BIT1 189 /// 190 /// A value of 1 indicates that a T/OS has not been established on the platform 191 /// 192 #define PTP_FIFO_ACC_ESTABLISH BIT0 193 194 /// 195 /// This field indicates that STS_DATA and STS_EXPECT are valid 196 /// 197 #define PTP_FIFO_STS_VALID BIT7 198 /// 199 /// When this bit is 1, TPM is in the Ready state, 200 /// indicating it is ready to receive a new command. 201 /// 202 #define PTP_FIFO_STS_READY BIT6 203 /// 204 /// Write a 1 to this bit to cause the TPM to execute that command. 205 /// 206 #define PTP_FIFO_STS_GO BIT5 207 /// 208 /// This bit indicates that the TPM has data available as a response. 209 /// 210 #define PTP_FIFO_STS_DATA BIT4 211 /// 212 /// The TPM sets this bit to a value of 1 when it expects another byte of data for a command. 213 /// 214 #define PTP_FIFO_STS_EXPECT BIT3 215 /// 216 /// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command. 217 /// 218 #define PTP_FIFO_STS_SELFTEST_DONE BIT2 219 /// 220 /// Writes a 1 to this bit to force the TPM to re-send the response. 221 /// 222 #define PTP_FIFO_STS_RETRY BIT1 223 224 /// 225 /// TPM Family Identifier. 226 /// 00: TPM 1.2 Family 227 /// 01: TPM 2.0 Family 228 /// 229 #define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 | BIT3) 230 #define PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET (2) 231 #define PTP_FIFO_STS_EX_TPM_FAMILY_TPM12 (0) 232 #define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20 (BIT2) 233 /// 234 /// A write of 1 after tpmGo and before dataAvail aborts the currently executing command, resulting in a response of TPM_RC_CANCELLED. 235 /// A write of 1 after dataAvail and before tpmGo is ignored by the TPM. 236 /// 237 #define PTP_FIFO_STS_EX_CANCEL BIT0 238 239 240 // 241 // PTP CRB definition 242 // 243 244 // 245 // Set structure alignment to 1-byte 246 // 247 #pragma pack (1) 248 249 // 250 // Register set map as specified in PTP specification Chapter 5 251 // 252 typedef struct { 253 /// 254 /// Used to determine current state of Locality of the TPM. 255 /// 256 UINT32 LocalityState; // 0 257 UINT8 Reserved1[4]; // 4 258 /// 259 /// Used to gain control of the TPM by this Locality. 260 /// 261 UINT32 LocalityControl; // 8 262 /// 263 /// Used to determine whether Locality has been granted or Seized. 264 /// 265 UINT32 LocalityStatus; // 0ch 266 UINT8 Reserved2[0x20]; // 10h 267 /// 268 /// Used to identify the Interface types supported by the TPM. 269 /// 270 UINT32 InterfaceId; // 30h 271 /// 272 /// Vendor ID 273 /// 274 UINT16 Vid; // 34h 275 /// 276 /// Device ID 277 /// 278 UINT16 Did; // 36h 279 /// 280 /// Optional Register used in low memory environments prior to CRB_DATA_BUFFER availability. 281 /// 282 UINT64 CrbControlExtension; // 38h 283 /// 284 /// Register used to initiate transactions for the CRB interface. 285 /// 286 UINT32 CrbControlRequest; // 40h 287 /// 288 /// Register used by the TPM to provide status of the CRB interface. 289 /// 290 UINT32 CrbControlStatus; // 44h 291 /// 292 /// Register used by software to cancel command processing. 293 /// 294 UINT32 CrbControlCancel; // 48h 295 /// 296 /// Register used to indicate presence of command or response data in the CRB buffer. 297 /// 298 UINT32 CrbControlStart; // 4Ch 299 /// 300 /// Register used to configure and respond to interrupts. 301 /// 302 UINT32 CrbInterruptEnable; // 50h 303 UINT32 CrbInterruptStatus; // 54h 304 /// 305 /// Size of the Command buffer. 306 /// 307 UINT32 CrbControlCommandSize; // 58h 308 /// 309 /// Command buffer start address 310 /// 311 UINT32 CrbControlCommandAddressLow; // 5Ch 312 UINT32 CrbControlCommandAddressHigh; // 60h 313 /// 314 /// Size of the Response buffer 315 /// 316 UINT32 CrbControlResponseSize; // 64h 317 /// 318 /// Address of the start of the Response buffer 319 /// 320 UINT64 CrbControlResponseAddrss; // 68h 321 UINT8 Reserved4[0x10]; // 70h 322 /// 323 /// Command/Response Data may be defined as large as 3968 (0xF80). 324 /// 325 UINT8 CrbDataBuffer[0xF80]; // 80h 326 } PTP_CRB_REGISTERS; 327 328 // 329 // Define pointer types used to access CRB registers on PTP 330 // 331 typedef PTP_CRB_REGISTERS *PTP_CRB_REGISTERS_PTR; 332 333 // 334 // Define bits of CRB Interface Identifier Register 335 // 336 typedef union { 337 struct { 338 UINT32 InterfaceType:4; 339 UINT32 InterfaceVersion:4; 340 UINT32 CapLocality:1; 341 UINT32 Reserved1:2; 342 UINT32 CapDataXferSizeSupport:2; 343 UINT32 CapFIFO:1; 344 UINT32 CapCRB:1; 345 UINT32 CapIFRes:2; 346 UINT32 InterfaceSelector:2; 347 UINT32 IntfSelLock:1; 348 UINT32 Reserved2:4; 349 UINT32 Rid:8; 350 } Bits; 351 UINT32 Uint32; 352 } PTP_CRB_INTERFACE_IDENTIFIER; 353 354 /// 355 /// InterfaceType 356 /// 357 #define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO 0x0 358 #define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB 0x1 359 #define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS 0xF 360 361 /// 362 /// InterfaceVersion 363 /// 364 #define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO 0x0 365 #define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB 0x1 366 367 /// 368 /// InterfaceSelector 369 /// 370 #define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_FIFO 0x0 371 #define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_CRB 0x1 372 373 // 374 // Define bits of Locality State Register 375 // 376 377 /// 378 /// This bit indicates whether all other bits of this register contain valid values, if it is a 1. 379 /// 380 #define PTP_CRB_LOCALITY_STATE_TPM_REG_VALID_STATUS BIT7 381 382 /// 383 /// 000 - Locality 0 384 /// 001 - Locality 1 385 /// 010 - Locality 2 386 /// 011 - Locality 3 387 /// 100 - Locality 4 388 /// 389 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 | BIT3 | BIT4) 390 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_0 (0) 391 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1 (BIT2) 392 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_2 (BIT3) 393 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 | BIT3) 394 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_4 (BIT4) 395 396 /// 397 /// A 0 indicates to the host that no locality is assigned. 398 /// A 1 indicates a locality has been assigned. 399 /// 400 #define PTP_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED BIT1 401 402 /// 403 /// The TPM clears this bit to 0 upon receipt of _TPM_Hash_End 404 /// The TPM sets this bit to a 1 when the TPM_LOC_CTRL_x.resetEstablishment field is set to 1. 405 /// 406 #define PTP_CRB_LOCALITY_STATE_TPM_ESTABLISHED BIT0 407 408 // 409 // Define bits of Locality Control Register 410 // 411 412 /// 413 /// Writes (1): Reset TPM_LOC_STATE_x.tpmEstablished bit if the write occurs from Locality 3 or 4. 414 /// 415 #define PTP_CRB_LOCALITY_CONTROL_RESET_ESTABLISHMENT_BIT BIT3 416 417 /// 418 /// Writes (1): The TPM gives control of the TPM to the locality setting this bit if it is the higher priority locality. 419 /// 420 #define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2 421 422 /// 423 /// Writes (1): The active Locality is done with the TPM. 424 /// 425 #define PTP_CRB_LOCALITY_CONTROL_RELINQUISH BIT1 426 427 /// 428 /// Writes (1): Interrupt the TPM and generate a locality arbitration algorithm. 429 /// 430 #define PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS BIT0 431 432 // 433 // Define bits of Locality Status Register 434 // 435 436 /// 437 /// 0: A higher locality has not initiated a Seize arbitration process. 438 /// 1: A higher locality has Seized the TPM from this locality. 439 /// 440 #define PTP_CRB_LOCALITY_STATUS_BEEN_SEIZED BIT1 441 442 /// 443 /// 0: Locality has not been granted to the TPM. 444 /// 1: Locality has been granted access to the TPM 445 /// 446 #define PTP_CRB_LOCALITY_STATUS_GRANTED BIT0 447 448 // 449 // Define bits of CRB Control Area Request Register 450 // 451 452 /// 453 /// Used by Software to indicate transition the TPM to and from the Idle state 454 /// 1: Set by Software to indicate response has been read from the response buffer and TPM can transition to Idle 455 /// 0: Cleared to 0 by TPM to acknowledge the request when TPM enters Idle state. 456 /// TPM SHALL complete this transition within TIMEOUT_C. 457 /// 458 #define PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE BIT1 459 460 /// 461 /// Used by Software to request the TPM transition to the Ready State. 462 /// 1: Set to 1 by Software to indicate the TPM should be ready to receive a command. 463 /// 0: Cleared to 0 by TPM to acknowledge the request. 464 /// TPM SHALL complete this transition within TIMEOUT_C. 465 /// 466 #define PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY BIT0 467 468 // 469 // Define bits of CRB Control Area Status Register 470 // 471 472 /// 473 /// Used by TPM to indicate it is in the Idle State 474 /// 1: Set by TPM when in the Idle State 475 /// 0: Cleared by TPM on receipt of TPM_CRB_CTRL_REQ_x.cmdReady when TPM transitions to the Ready State. 476 /// SHALL be cleared by TIMEOUT_C. 477 /// 478 #define PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE BIT1 479 480 /// 481 /// Used by the TPM to indicate current status. 482 /// 1: Set by TPM to indicate a FATAL Error 483 /// 0: Indicates TPM is operational 484 /// 485 #define PTP_CRB_CONTROL_AREA_STATUS_TPM_STATUS BIT0 486 487 // 488 // Define bits of CRB Control Cancel Register 489 // 490 491 /// 492 /// Used by software to cancel command processing Reads return correct value 493 /// Writes (0000 0001h): Cancel a command 494 /// Writes (0000 0000h): Clears field when command has been cancelled 495 /// 496 #define PTP_CRB_CONTROL_CANCEL BIT0 497 498 // 499 // Define bits of CRB Control Start Register 500 // 501 502 /// 503 /// When set by software, indicates a command is ready for processing. 504 /// Writes (0000 0001h): TPM transitions to Command Execution 505 /// Writes (0000 0000h): TPM clears this field and transitions to Command Completion 506 /// 507 #define PTP_CRB_CONTROL_START BIT0 508 509 // 510 // Restore original structure alignment 511 // 512 #pragma pack () 513 514 // 515 // Default TimeOut value 516 // 517 #define PTP_TIMEOUT_A (750 * 1000) // 750ms 518 #define PTP_TIMEOUT_B (2000 * 1000) // 2s 519 #define PTP_TIMEOUT_C (200 * 1000) // 200ms 520 #define PTP_TIMEOUT_D (30 * 1000) // 30ms 521 522 #endif