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2 Copyright (C) 2016 Marvell International Ltd.
3 
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9 are permitted provided that the following conditions are met:
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11 * Redistributions of source code must retain the above copyright notice,
12   this list of conditions and the following disclaimer.
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14 * Redistributions in binary form must reproduce the above copyright
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18 * Neither the name of Marvell nor the names of its contributors may be
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22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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32 
33 *******************************************************************************/
34 #ifndef __SPI_MASTER_H__
35 #define __SPI_MASTER_H__
36 
37 #include <Library/IoLib.h>
38 #include <Library/PcdLib.h>
39 #include <Library/UefiLib.h>
40 #include <Library/DebugLib.h>
41 #include <Library/MemoryAllocationLib.h>
42 #include <Uefi/UefiBaseType.h>
43 #include <Library/BaseMemoryLib.h>
44 #include <Library/UefiBootServicesTableLib.h>
45 
46 #include <Protocol/Spi.h>
47 
48 #define SPI_MASTER_SIGNATURE                      SIGNATURE_32 ('M', 'S', 'P', 'I')
49 #define SPI_MASTER_FROM_SPI_MASTER_PROTOCOL(a)  CR (a, SPI_MASTER, SpiMasterProtocol, SPI_MASTER_SIGNATURE)
50 
51 // Marvell Flash Device Controller Registers
52 #define SPI_CTRL_REG                    (0x00)
53 #define SPI_CONF_REG                    (0x04)
54 #define SPI_DATA_OUT_REG                (0x08)
55 #define SPI_DATA_IN_REG                 (0x0c)
56 #define SPI_INT_CAUSE_REG               (0x10)
57 
58 // Serial Memory Interface Control Register Masks
59 #define SPI_CS_NUM_OFFSET               2
60 #define SPI_CS_NUM_MASK                 (0x7 << SPI_CS_NUM_OFFSET)
61 #define SPI_MEM_READY_MASK              (0x1 << 1)
62 #define SPI_CS_EN_MASK                  (0x1 << 0)
63 
64 // Serial Memory Interface Configuration Register Masks
65 #define SPI_BYTE_LENGTH_OFFSET          5
66 #define SPI_BYTE_LENGTH                 (0x1  << SPI_BYTE_LENGTH_OFFSET)
67 #define SPI_CPOL_OFFSET                 11
68 #define SPI_CPOL_MASK                   (0x1 << SPI_CPOL_OFFSET)
69 #define SPI_CPHA_OFFSET                 12
70 #define SPI_CPHA_MASK                  (0x1 << SPI_CPHA_OFFSET)
71 #define SPI_TXLSBF_OFFSET               13
72 #define SPI_TXLSBF_MASK                 (0x1 << SPI_TXLSBF_OFFSET)
73 #define SPI_RXLSBF_OFFSET               14
74 #define SPI_RXLSBF_MASK                 (0x1 << SPI_RXLSBF_OFFSET)
75 
76 #define SPI_SPR_OFFSET                  0
77 #define SPI_SPR_MASK                    (0xf << SPI_SPR_OFFSET)
78 #define SPI_SPPR_0_OFFSET               4
79 #define SPI_SPPR_0_MASK                 (0x1 << SPI_SPPR_0_OFFSET)
80 #define SPI_SPPR_HI_OFFSET              6
81 #define SPI_SPPR_HI_MASK                (0x3 << SPI_SPPR_HI_OFFSET)
82 
83 #define SPI_TRANSFER_BEGIN              0x01  // Assert CS before transfer
84 #define SPI_TRANSFER_END                0x02  // Deassert CS after transfers
85 
86 #define SPI_TIMEOUT                     100000
87 
88 typedef struct {
89   MARVELL_SPI_MASTER_PROTOCOL SpiMasterProtocol;
90   UINTN                   Signature;
91   EFI_HANDLE              Handle;
92   EFI_LOCK                Lock;
93 } SPI_MASTER;
94 
95 EFI_STATUS
96 EFIAPI
97 MvSpiTransfer (
98   IN MARVELL_SPI_MASTER_PROTOCOL *This,
99   IN SPI_DEVICE *Slave,
100   IN UINTN DataByteCount,
101   IN VOID *DataOut,
102   IN VOID *DataIn,
103   IN UINTN Flag
104   );
105 
106 EFI_STATUS
107 EFIAPI
108 MvSpiReadWrite (
109   IN  MARVELL_SPI_MASTER_PROTOCOL *This,
110   IN  SPI_DEVICE *Slave,
111   IN  UINT8 *Cmd,
112   IN  UINTN CmdSize,
113   IN  UINT8 *DataOut,
114   OUT UINT8 *DataIn,
115   IN  UINTN DataSize
116   );
117 
118 EFI_STATUS
119 EFIAPI
120 MvSpiInit (
121   IN MARVELL_SPI_MASTER_PROTOCOL     * This
122   );
123 
124 SPI_DEVICE *
125 EFIAPI
126 MvSpiSetupSlave (
127   IN MARVELL_SPI_MASTER_PROTOCOL     * This,
128   IN UINTN Cs,
129   IN SPI_MODE Mode
130   );
131 
132 EFI_STATUS
133 EFIAPI
134 MvSpiFreeSlave (
135   IN SPI_DEVICE *Slave
136   );
137 
138 EFI_STATUS
139 EFIAPI
140 SpiMasterEntryPoint (
141   IN EFI_HANDLE       ImageHandle,
142   IN EFI_SYSTEM_TABLE *SystemTable
143   );
144 
145 #endif // __SPI_MASTER_H__
146