1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __ARCH_H__ 8 #define __ARCH_H__ 9 10 #include <utils_def.h> 11 12 /******************************************************************************* 13 * MIDR bit definitions 14 ******************************************************************************/ 15 #define MIDR_IMPL_MASK 0xff 16 #define MIDR_IMPL_SHIFT 24 17 #define MIDR_VAR_SHIFT 20 18 #define MIDR_VAR_BITS 4 19 #define MIDR_REV_SHIFT 0 20 #define MIDR_REV_BITS 4 21 #define MIDR_PN_MASK 0xfff 22 #define MIDR_PN_SHIFT 4 23 24 /******************************************************************************* 25 * MPIDR macros 26 ******************************************************************************/ 27 #define MPIDR_MT_MASK (1 << 24) 28 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 29 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 30 #define MPIDR_AFFINITY_BITS 8 31 #define MPIDR_AFFLVL_MASK 0xff 32 #define MPIDR_AFFLVL_SHIFT 3 33 #define MPIDR_AFF0_SHIFT 0 34 #define MPIDR_AFF1_SHIFT 8 35 #define MPIDR_AFF2_SHIFT 16 36 #define MPIDR_AFFINITY_MASK 0x00ffffff 37 #define MPIDR_AFFLVL0 0 38 #define MPIDR_AFFLVL1 1 39 #define MPIDR_AFFLVL2 2 40 41 #define MPIDR_AFFLVL0_VAL(mpidr) \ 42 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 43 #define MPIDR_AFFLVL1_VAL(mpidr) \ 44 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 45 #define MPIDR_AFFLVL2_VAL(mpidr) \ 46 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 47 #define MPIDR_AFFLVL3_VAL(mpidr) 0 48 49 /* 50 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 51 * add one while using this macro to define array sizes. 52 */ 53 #define MPIDR_MAX_AFFLVL 2 54 55 /* Data Cache set/way op type defines */ 56 #define DC_OP_ISW 0x0 57 #define DC_OP_CISW 0x1 58 #define DC_OP_CSW 0x2 59 60 /******************************************************************************* 61 * Generic timer memory mapped registers & offsets 62 ******************************************************************************/ 63 #define CNTCR_OFF 0x000 64 #define CNTFID_OFF 0x020 65 66 #define CNTCR_EN (1 << 0) 67 #define CNTCR_HDBG (1 << 1) 68 #define CNTCR_FCREQ(x) ((x) << 8) 69 70 /******************************************************************************* 71 * System register bit definitions 72 ******************************************************************************/ 73 /* CLIDR definitions */ 74 #define LOUIS_SHIFT 21 75 #define LOC_SHIFT 24 76 #define CLIDR_FIELD_WIDTH 3 77 78 /* CSSELR definitions */ 79 #define LEVEL_SHIFT 1 80 81 /* ID_PFR1 definitions */ 82 #define ID_PFR1_VIRTEXT_SHIFT 12 83 #define ID_PFR1_VIRTEXT_MASK 0xf 84 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 85 & ID_PFR1_VIRTEXT_MASK) 86 #define ID_PFR1_GIC_SHIFT 28 87 #define ID_PFR1_GIC_MASK 0xf 88 89 /* SCTLR definitions */ 90 #define SCTLR_RES1 ((1 << 23) | (1 << 22) | (1 << 11) | (1 << 4) | \ 91 (1 << 3)) 92 #define SCTLR_M_BIT (1 << 0) 93 #define SCTLR_A_BIT (1 << 1) 94 #define SCTLR_C_BIT (1 << 2) 95 #define SCTLR_CP15BEN_BIT (1 << 5) 96 #define SCTLR_ITD_BIT (1 << 7) 97 #define SCTLR_I_BIT (1 << 12) 98 #define SCTLR_V_BIT (1 << 13) 99 #define SCTLR_NTWI_BIT (1 << 16) 100 #define SCTLR_NTWE_BIT (1 << 18) 101 #define SCTLR_WXN_BIT (1 << 19) 102 #define SCTLR_UWXN_BIT (1 << 20) 103 #define SCTLR_EE_BIT (1 << 25) 104 #define SCTLR_TRE_BIT (1 << 28) 105 #define SCTLR_AFE_BIT (1 << 29) 106 #define SCTLR_TE_BIT (1 << 30) 107 #define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \ 108 SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT) 109 110 /* SDCR definitions */ 111 #define SDCR_SPD(x) ((x) << 14) 112 #define SDCR_SPD_LEGACY 0x0 113 #define SDCR_SPD_DISABLE 0x2 114 #define SDCR_SPD_ENABLE 0x3 115 #define SDCR_RESET_VAL 0x0 116 117 #if !ERROR_DEPRECATED 118 #define SDCR_DEF_VAL SDCR_SPD(SDCR_SPD_DISABLE) 119 #endif 120 121 /* HSCTLR definitions */ 122 #define HSCTLR_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) \ 123 | (1 << 18) | (1 << 16) | (1 << 11) | (1 << 4) \ 124 | (1 << 3)) 125 #define HSCTLR_M_BIT (1 << 0) 126 #define HSCTLR_A_BIT (1 << 1) 127 #define HSCTLR_C_BIT (1 << 2) 128 #define HSCTLR_CP15BEN_BIT (1 << 5) 129 #define HSCTLR_ITD_BIT (1 << 7) 130 #define HSCTLR_SED_BIT (1 << 8) 131 #define HSCTLR_I_BIT (1 << 12) 132 #define HSCTLR_WXN_BIT (1 << 19) 133 #define HSCTLR_EE_BIT (1 << 25) 134 #define HSCTLR_TE_BIT (1 << 30) 135 136 /* CPACR definitions */ 137 #define CPACR_FPEN(x) ((x) << 20) 138 #define CPACR_FP_TRAP_PL0 0x1 139 #define CPACR_FP_TRAP_ALL 0x2 140 #define CPACR_FP_TRAP_NONE 0x3 141 142 /* SCR definitions */ 143 #define SCR_TWE_BIT (1 << 13) 144 #define SCR_TWI_BIT (1 << 12) 145 #define SCR_SIF_BIT (1 << 9) 146 #define SCR_HCE_BIT (1 << 8) 147 #define SCR_SCD_BIT (1 << 7) 148 #define SCR_NET_BIT (1 << 6) 149 #define SCR_AW_BIT (1 << 5) 150 #define SCR_FW_BIT (1 << 4) 151 #define SCR_EA_BIT (1 << 3) 152 #define SCR_FIQ_BIT (1 << 2) 153 #define SCR_IRQ_BIT (1 << 1) 154 #define SCR_NS_BIT (1 << 0) 155 #define SCR_VALID_BIT_MASK 0x33ff 156 #define SCR_RESET_VAL 0x0 157 158 #define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT) 159 160 /* HCR definitions */ 161 #define HCR_AMO_BIT (1 << 5) 162 #define HCR_IMO_BIT (1 << 4) 163 #define HCR_FMO_BIT (1 << 3) 164 #define HCR_RESET_VAL 0x0 165 166 /* CNTHCTL definitions */ 167 #define CNTHCTL_RESET_VAL 0x0 168 #define PL1PCEN_BIT (1 << 1) 169 #define PL1PCTEN_BIT (1 << 0) 170 171 /* CNTKCTL definitions */ 172 #define PL0PTEN_BIT (1 << 9) 173 #define PL0VTEN_BIT (1 << 8) 174 #define PL0PCTEN_BIT (1 << 0) 175 #define PL0VCTEN_BIT (1 << 1) 176 #define EVNTEN_BIT (1 << 2) 177 #define EVNTDIR_BIT (1 << 3) 178 #define EVNTI_SHIFT 4 179 #define EVNTI_MASK 0xf 180 181 /* HCPTR definitions */ 182 #define HCPTR_RES1 ((1 << 13) | (1<<12) | 0x3ff) 183 #define TCPAC_BIT (1 << 31) 184 #define TTA_BIT (1 << 20) 185 #define TCP11_BIT (1 << 10) 186 #define TCP10_BIT (1 << 10) 187 #define HCPTR_RESET_VAL HCPTR_RES1 188 189 /* VTTBR defintions */ 190 #define VTTBR_RESET_VAL ULL(0x0) 191 #define VTTBR_VMID_MASK ULL(0xff) 192 #define VTTBR_VMID_SHIFT 48 193 #define VTTBR_BADDR_MASK 0xffffffffffff 194 #define VTTBR_BADDR_SHIFT 0 195 196 /* HDCR definitions */ 197 #define HDCR_RESET_VAL 0x0 198 199 /* HSTR definitions */ 200 #define HSTR_RESET_VAL 0x0 201 202 /* CNTHP_CTL definitions */ 203 #define CNTHP_CTL_RESET_VAL 0x0 204 205 /* NASCR definitions */ 206 #define NSASEDIS_BIT (1 << 15) 207 #define NSTRCDIS_BIT (1 << 20) 208 /* NOTE: correct typo in the definitions */ 209 #if !ERROR_DEPRECATED 210 #define NASCR_CP11_BIT (1 << 11) 211 #define NASCR_CP10_BIT (1 << 10) 212 #endif 213 #define NSACR_CP11_BIT (1 << 11) 214 #define NSACR_CP10_BIT (1 << 10) 215 #define NSACR_IMP_DEF_MASK (0x7 << 16) 216 #define NSACR_ENABLE_FP_ACCESS (NSACR_CP11_BIT | NSACR_CP10_BIT) 217 #define NSACR_RESET_VAL 0x0 218 219 /* CPACR definitions */ 220 #define ASEDIS_BIT (1 << 31) 221 #define TRCDIS_BIT (1 << 28) 222 #define CPACR_CP11_SHIFT 22 223 #define CPACR_CP10_SHIFT 20 224 #define CPACR_ENABLE_FP_ACCESS (0x3 << CPACR_CP11_SHIFT |\ 225 0x3 << CPACR_CP10_SHIFT) 226 #define CPACR_RESET_VAL 0x0 227 228 /* FPEXC definitions */ 229 #define FPEXC_RES1 ((1 << 10) | (1 << 9) | (1 << 8)) 230 #define FPEXC_EN_BIT (1 << 30) 231 #define FPEXC_RESET_VAL FPEXC_RES1 232 233 /* SPSR/CPSR definitions */ 234 #define SPSR_FIQ_BIT (1 << 0) 235 #define SPSR_IRQ_BIT (1 << 1) 236 #define SPSR_ABT_BIT (1 << 2) 237 #define SPSR_AIF_SHIFT 6 238 #define SPSR_AIF_MASK 0x7 239 240 #define SPSR_E_SHIFT 9 241 #define SPSR_E_MASK 0x1 242 #define SPSR_E_LITTLE 0 243 #define SPSR_E_BIG 1 244 245 #define SPSR_T_SHIFT 5 246 #define SPSR_T_MASK 0x1 247 #define SPSR_T_ARM 0 248 #define SPSR_T_THUMB 1 249 250 #define SPSR_MODE_SHIFT 0 251 #define SPSR_MODE_MASK 0x7 252 253 254 #define DISABLE_ALL_EXCEPTIONS \ 255 (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT) 256 257 /* 258 * TTBCR definitions 259 */ 260 /* The ARM Trusted Firmware uses the long descriptor format */ 261 #define TTBCR_EAE_BIT (1 << 31) 262 263 #define TTBCR_SH1_NON_SHAREABLE (0x0 << 28) 264 #define TTBCR_SH1_OUTER_SHAREABLE (0x2 << 28) 265 #define TTBCR_SH1_INNER_SHAREABLE (0x3 << 28) 266 267 #define TTBCR_RGN1_OUTER_NC (0x0 << 26) 268 #define TTBCR_RGN1_OUTER_WBA (0x1 << 26) 269 #define TTBCR_RGN1_OUTER_WT (0x2 << 26) 270 #define TTBCR_RGN1_OUTER_WBNA (0x3 << 26) 271 272 #define TTBCR_RGN1_INNER_NC (0x0 << 24) 273 #define TTBCR_RGN1_INNER_WBA (0x1 << 24) 274 #define TTBCR_RGN1_INNER_WT (0x2 << 24) 275 #define TTBCR_RGN1_INNER_WBNA (0x3 << 24) 276 277 #define TTBCR_EPD1_BIT (1 << 23) 278 #define TTBCR_A1_BIT (1 << 22) 279 280 #define TTBCR_T1SZ_SHIFT 16 281 #define TTBCR_T1SZ_MASK (0x7) 282 #define TTBCR_TxSZ_MIN 0 283 #define TTBCR_TxSZ_MAX 7 284 285 #define TTBCR_SH0_NON_SHAREABLE (0x0 << 12) 286 #define TTBCR_SH0_OUTER_SHAREABLE (0x2 << 12) 287 #define TTBCR_SH0_INNER_SHAREABLE (0x3 << 12) 288 289 #define TTBCR_RGN0_OUTER_NC (0x0 << 10) 290 #define TTBCR_RGN0_OUTER_WBA (0x1 << 10) 291 #define TTBCR_RGN0_OUTER_WT (0x2 << 10) 292 #define TTBCR_RGN0_OUTER_WBNA (0x3 << 10) 293 294 #define TTBCR_RGN0_INNER_NC (0x0 << 8) 295 #define TTBCR_RGN0_INNER_WBA (0x1 << 8) 296 #define TTBCR_RGN0_INNER_WT (0x2 << 8) 297 #define TTBCR_RGN0_INNER_WBNA (0x3 << 8) 298 299 #define TTBCR_EPD0_BIT (1 << 7) 300 #define TTBCR_T0SZ_SHIFT 0 301 #define TTBCR_T0SZ_MASK (0x7) 302 303 #define MODE_RW_SHIFT 0x4 304 #define MODE_RW_MASK 0x1 305 #define MODE_RW_32 0x1 306 307 #define MODE32_SHIFT 0 308 #define MODE32_MASK 0x1f 309 #define MODE32_usr 0x10 310 #define MODE32_fiq 0x11 311 #define MODE32_irq 0x12 312 #define MODE32_svc 0x13 313 #define MODE32_mon 0x16 314 #define MODE32_abt 0x17 315 #define MODE32_hyp 0x1a 316 #define MODE32_und 0x1b 317 #define MODE32_sys 0x1f 318 319 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 320 321 #define SPSR_MODE32(mode, isa, endian, aif) \ 322 (MODE_RW_32 << MODE_RW_SHIFT | \ 323 ((mode) & MODE32_MASK) << MODE32_SHIFT | \ 324 ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \ 325 ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \ 326 ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) 327 328 /* 329 * TTBR definitions 330 */ 331 #define TTBR_CNP_BIT 0x1 332 333 /* 334 * CTR definitions 335 */ 336 #define CTR_CWG_SHIFT 24 337 #define CTR_CWG_MASK 0xf 338 #define CTR_ERG_SHIFT 20 339 #define CTR_ERG_MASK 0xf 340 #define CTR_DMINLINE_SHIFT 16 341 #define CTR_DMINLINE_WIDTH 4 342 #define CTR_DMINLINE_MASK ((1 << 4) - 1) 343 #define CTR_L1IP_SHIFT 14 344 #define CTR_L1IP_MASK 0x3 345 #define CTR_IMINLINE_SHIFT 0 346 #define CTR_IMINLINE_MASK 0xf 347 348 #define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */ 349 350 /* PMCR definitions */ 351 #define PMCR_N_SHIFT 11 352 #define PMCR_N_MASK 0x1f 353 #define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT) 354 #define PMCR_LC_BIT (1 << 6) 355 #define PMCR_DP_BIT (1 << 5) 356 357 /******************************************************************************* 358 * Definitions of register offsets, fields and macros for CPU system 359 * instructions. 360 ******************************************************************************/ 361 362 #define TLBI_ADDR_SHIFT 0 363 #define TLBI_ADDR_MASK 0xFFFFF000 364 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 365 366 /******************************************************************************* 367 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 368 * system level implementation of the Generic Timer. 369 ******************************************************************************/ 370 #define CNTNSAR 0x4 371 #define CNTNSAR_NS_SHIFT(x) (x) 372 373 #define CNTACR_BASE(x) (0x40 + ((x) << 2)) 374 #define CNTACR_RPCT_SHIFT 0x0 375 #define CNTACR_RVCT_SHIFT 0x1 376 #define CNTACR_RFRQ_SHIFT 0x2 377 #define CNTACR_RVOFF_SHIFT 0x3 378 #define CNTACR_RWVT_SHIFT 0x4 379 #define CNTACR_RWPT_SHIFT 0x5 380 381 /* MAIR macros */ 382 #define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << 3)) 383 #define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - 3) << 3)) 384 385 /* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */ 386 #define SCR p15, 0, c1, c1, 0 387 #define SCTLR p15, 0, c1, c0, 0 388 #define SDCR p15, 0, c1, c3, 1 389 #define MPIDR p15, 0, c0, c0, 5 390 #define MIDR p15, 0, c0, c0, 0 391 #define VBAR p15, 0, c12, c0, 0 392 #define MVBAR p15, 0, c12, c0, 1 393 #define NSACR p15, 0, c1, c1, 2 394 #define CPACR p15, 0, c1, c0, 2 395 #define DCCIMVAC p15, 0, c7, c14, 1 396 #define DCCMVAC p15, 0, c7, c10, 1 397 #define DCIMVAC p15, 0, c7, c6, 1 398 #define DCCISW p15, 0, c7, c14, 2 399 #define DCCSW p15, 0, c7, c10, 2 400 #define DCISW p15, 0, c7, c6, 2 401 #define CTR p15, 0, c0, c0, 1 402 #define CNTFRQ p15, 0, c14, c0, 0 403 #define ID_PFR1 p15, 0, c0, c1, 1 404 #define MAIR0 p15, 0, c10, c2, 0 405 #define MAIR1 p15, 0, c10, c2, 1 406 #define TTBCR p15, 0, c2, c0, 2 407 #define TTBR0 p15, 0, c2, c0, 0 408 #define TTBR1 p15, 0, c2, c0, 1 409 #define TLBIALL p15, 0, c8, c7, 0 410 #define TLBIALLIS p15, 0, c8, c3, 0 411 #define TLBIMVA p15, 0, c8, c7, 1 412 #define TLBIMVAA p15, 0, c8, c7, 3 413 #define TLBIMVAAIS p15, 0, c8, c3, 3 414 #define BPIALLIS p15, 0, c7, c1, 6 415 #define HSCTLR p15, 4, c1, c0, 0 416 #define HCR p15, 4, c1, c1, 0 417 #define HCPTR p15, 4, c1, c1, 2 418 #define HSTR p15, 4, c1, c1, 3 419 #define CNTHCTL p15, 4, c14, c1, 0 420 #define CNTKCTL p15, 0, c14, c1, 0 421 #define VPIDR p15, 4, c0, c0, 0 422 #define VMPIDR p15, 4, c0, c0, 5 423 #define ISR p15, 0, c12, c1, 0 424 #define CLIDR p15, 1, c0, c0, 1 425 #define CSSELR p15, 2, c0, c0, 0 426 #define CCSIDR p15, 1, c0, c0, 0 427 #define DBGOSDLR p14, 0, c1, c3, 4 428 429 /* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ 430 #define HDCR p15, 4, c1, c1, 1 431 #define PMCR p15, 0, c9, c12, 0 432 #define CNTHP_CTL p15, 4, c14, c2, 1 433 434 /* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ 435 #define ICC_IAR1 p15, 0, c12, c12, 0 436 #define ICC_IAR0 p15, 0, c12, c8, 0 437 #define ICC_EOIR1 p15, 0, c12, c12, 1 438 #define ICC_EOIR0 p15, 0, c12, c8, 1 439 #define ICC_HPPIR1 p15, 0, c12, c12, 2 440 #define ICC_HPPIR0 p15, 0, c12, c8, 2 441 #define ICC_BPR1 p15, 0, c12, c12, 3 442 #define ICC_BPR0 p15, 0, c12, c8, 3 443 #define ICC_DIR p15, 0, c12, c11, 1 444 #define ICC_PMR p15, 0, c4, c6, 0 445 #define ICC_RPR p15, 0, c12, c11, 3 446 #define ICC_CTLR p15, 0, c12, c12, 4 447 #define ICC_MCTLR p15, 6, c12, c12, 4 448 #define ICC_SRE p15, 0, c12, c12, 5 449 #define ICC_HSRE p15, 4, c12, c9, 5 450 #define ICC_MSRE p15, 6, c12, c12, 5 451 #define ICC_IGRPEN0 p15, 0, c12, c12, 6 452 #define ICC_IGRPEN1 p15, 0, c12, c12, 7 453 #define ICC_MGRPEN1 p15, 6, c12, c12, 7 454 455 /* 64 bit system register defines The format is: coproc, opt1, CRm */ 456 #define TTBR0_64 p15, 0, c2 457 #define TTBR1_64 p15, 1, c2 458 #define CNTVOFF_64 p15, 4, c14 459 #define VTTBR_64 p15, 6, c2 460 #define CNTPCT_64 p15, 0, c14 461 462 /* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */ 463 #define ICC_SGI1R_EL1_64 p15, 0, c12 464 #define ICC_ASGI1R_EL1_64 p15, 1, c12 465 #define ICC_SGI0R_EL1_64 p15, 2, c12 466 467 /******************************************************************************* 468 * Definitions of MAIR encodings for device and normal memory 469 ******************************************************************************/ 470 /* 471 * MAIR encodings for device memory attributes. 472 */ 473 #define MAIR_DEV_nGnRnE U(0x0) 474 #define MAIR_DEV_nGnRE U(0x4) 475 #define MAIR_DEV_nGRE U(0x8) 476 #define MAIR_DEV_GRE U(0xc) 477 478 /* 479 * MAIR encodings for normal memory attributes. 480 * 481 * Cache Policy 482 * WT: Write Through 483 * WB: Write Back 484 * NC: Non-Cacheable 485 * 486 * Transient Hint 487 * NTR: Non-Transient 488 * TR: Transient 489 * 490 * Allocation Policy 491 * RA: Read Allocate 492 * WA: Write Allocate 493 * RWA: Read and Write Allocate 494 * NA: No Allocation 495 */ 496 #define MAIR_NORM_WT_TR_WA U(0x1) 497 #define MAIR_NORM_WT_TR_RA U(0x2) 498 #define MAIR_NORM_WT_TR_RWA U(0x3) 499 #define MAIR_NORM_NC U(0x4) 500 #define MAIR_NORM_WB_TR_WA U(0x5) 501 #define MAIR_NORM_WB_TR_RA U(0x6) 502 #define MAIR_NORM_WB_TR_RWA U(0x7) 503 #define MAIR_NORM_WT_NTR_NA U(0x8) 504 #define MAIR_NORM_WT_NTR_WA U(0x9) 505 #define MAIR_NORM_WT_NTR_RA U(0xa) 506 #define MAIR_NORM_WT_NTR_RWA U(0xb) 507 #define MAIR_NORM_WB_NTR_NA U(0xc) 508 #define MAIR_NORM_WB_NTR_WA U(0xd) 509 #define MAIR_NORM_WB_NTR_RA U(0xe) 510 #define MAIR_NORM_WB_NTR_RWA U(0xf) 511 512 #define MAIR_NORM_OUTER_SHIFT 4 513 514 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 515 516 #endif /* __ARCH_H__ */ 517