1 /*
2  * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef __ZYNQMP_DEF_H__
8 #define __ZYNQMP_DEF_H__
9 
10 #include <common_def.h>
11 
12 #define ZYNQMP_CONSOLE_ID_cadence	1
13 #define ZYNQMP_CONSOLE_ID_cadence0	1
14 #define ZYNQMP_CONSOLE_ID_cadence1	2
15 #define ZYNQMP_CONSOLE_ID_dcc		3
16 
17 #define ZYNQMP_CONSOLE_IS(con)	(ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE)
18 
19 /* Firmware Image Package */
20 #define ZYNQMP_PRIMARY_CPU		0
21 
22 /* Memory location options for Shared data and TSP in ZYNQMP */
23 #define ZYNQMP_IN_TRUSTED_SRAM		0
24 #define ZYNQMP_IN_TRUSTED_DRAM		1
25 
26 /*******************************************************************************
27  * ZYNQMP memory map related constants
28  ******************************************************************************/
29 /* Aggregate of all devices in the first GB */
30 #define DEVICE0_BASE		0xFF000000
31 #define DEVICE0_SIZE		0x00E00000
32 #define DEVICE1_BASE		0xF9000000
33 #define DEVICE1_SIZE		0x00800000
34 
35 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
36 #define CRF_APB_BASE		0xFD1A0000
37 #define CRF_APB_SIZE		0x00600000
38 
39 /* CRF registers and bitfields */
40 #define CRF_APB_RST_FPD_APU	(CRF_APB_BASE + 0X00000104)
41 
42 #define CRF_APB_RST_FPD_APU_ACPU_RESET		(1 << 0)
43 #define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET	(1 << 10)
44 
45 /* CRL registers and bitfields */
46 #define CRL_APB_BASE			0xFF5E0000
47 #define CRL_APB_RPLL_CTRL		(CRL_APB_BASE + 0x30)
48 #define CRL_APB_BOOT_MODE_USER		(CRL_APB_BASE + 0x200)
49 #define CRL_APB_RESET_CTRL		(CRL_APB_BASE + 0x218)
50 
51 #define CRL_APB_RPLL_CTRL_BYPASS	(1 << 3)
52 
53 #define CRL_APB_RESET_CTRL_SOFT_RESET	(1 << 4)
54 
55 #define CRL_APB_BOOT_MODE_MASK		(0xf << 0)
56 #define ZYNQMP_BOOTMODE_JTAG		0
57 
58 /* system counter registers and bitfields */
59 #define IOU_SCNTRS_BASE			0xFF260000
60 #define IOU_SCNTRS_BASEFREQ		(IOU_SCNTRS_BASE + 0x20)
61 
62 /* APU registers and bitfields */
63 #define APU_BASE		0xFD5C0000
64 #define APU_CONFIG_0		(APU_BASE + 0x20)
65 #define APU_RVBAR_L_0		(APU_BASE + 0x40)
66 #define APU_RVBAR_H_0		(APU_BASE + 0x44)
67 #define APU_PWRCTL		(APU_BASE + 0x90)
68 
69 #define APU_CONFIG_0_VINITHI_SHIFT	8
70 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK		1
71 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK		2
72 #define APU_2_PWRCTL_CPUPWRDWNREQ_MASK		4
73 #define APU_3_PWRCTL_CPUPWRDWNREQ_MASK		8
74 
75 /* PMU registers and bitfields */
76 #define PMU_GLOBAL_BASE			0xFFD80000
77 #define PMU_GLOBAL_CNTRL		(PMU_GLOBAL_BASE + 0)
78 #define PMU_GLOBAL_GEN_STORAGE6		(PMU_GLOBAL_BASE + 0x48)
79 #define PMU_GLOBAL_REQ_PWRUP_STATUS	(PMU_GLOBAL_BASE + 0x110)
80 #define PMU_GLOBAL_REQ_PWRUP_EN		(PMU_GLOBAL_BASE + 0x118)
81 #define PMU_GLOBAL_REQ_PWRUP_DIS	(PMU_GLOBAL_BASE + 0x11c)
82 #define PMU_GLOBAL_REQ_PWRUP_TRIG	(PMU_GLOBAL_BASE + 0x120)
83 
84 #define PMU_GLOBAL_CNTRL_FW_IS_PRESENT	(1 << 4)
85 
86 /*******************************************************************************
87  * CCI-400 related constants
88  ******************************************************************************/
89 #define PLAT_ARM_CCI_BASE		0xFD6E0000
90 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX	3
91 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX	4
92 
93 /*******************************************************************************
94  * GIC-400 & interrupt handling related constants
95  ******************************************************************************/
96 #define BASE_GICD_BASE		0xF9010000
97 #define BASE_GICC_BASE		0xF9020000
98 #define BASE_GICH_BASE		0xF9040000
99 #define BASE_GICV_BASE		0xF9060000
100 
101 #define ARM_IRQ_SEC_PHY_TIMER		29
102 
103 #define ARM_IRQ_SEC_SGI_0		8
104 #define ARM_IRQ_SEC_SGI_1		9
105 #define ARM_IRQ_SEC_SGI_2		10
106 #define ARM_IRQ_SEC_SGI_3		11
107 #define ARM_IRQ_SEC_SGI_4		12
108 #define ARM_IRQ_SEC_SGI_5		13
109 #define ARM_IRQ_SEC_SGI_6		14
110 #define ARM_IRQ_SEC_SGI_7		15
111 
112 #define MAX_INTR_EL3			128
113 
114 /*******************************************************************************
115  * UART related constants
116  ******************************************************************************/
117 #define ZYNQMP_UART0_BASE		0xFF000000
118 #define ZYNQMP_UART1_BASE		0xFF010000
119 
120 #if ZYNQMP_CONSOLE_IS(cadence)
121 # define ZYNQMP_UART_BASE	ZYNQMP_UART0_BASE
122 #elif ZYNQMP_CONSOLE_IS(cadence1)
123 # define ZYNQMP_UART_BASE	ZYNQMP_UART1_BASE
124 #else
125 # error "invalid ZYNQMP_CONSOLE"
126 #endif
127 
128 #define PLAT_ARM_CRASH_UART_BASE	ZYNQMP_UART_BASE
129 /* impossible to call C routine how it is done now - hardcode any value */
130 #define	PLAT_ARM_CRASH_UART_CLK_IN_HZ	100000000 /* FIXME */
131 
132 /* Must be non zero */
133 #define ZYNQMP_UART_BAUDRATE	115200
134 #define ARM_CONSOLE_BAUDRATE	ZYNQMP_UART_BAUDRATE
135 
136 /* Silicon version detection */
137 #define ZYNQMP_SILICON_VER_MASK		0xF000
138 #define ZYNQMP_SILICON_VER_SHIFT	12
139 #define ZYNQMP_CSU_VERSION_SILICON	0
140 #define ZYNQMP_CSU_VERSION_EP108	1
141 #define ZYNQMP_CSU_VERSION_VELOCE	2
142 #define ZYNQMP_CSU_VERSION_QEMU		3
143 
144 #define ZYNQMP_RTL_VER_MASK		0xFF0
145 #define ZYNQMP_RTL_VER_SHIFT		4
146 
147 #define ZYNQMP_PS_VER_MASK		0xF
148 #define ZYNQMP_PS_VER_SHIFT		0
149 
150 #define ZYNQMP_CSU_BASEADDR		0xFFCA0000
151 #define ZYNQMP_CSU_IDCODE_OFFSET	0x40
152 
153 #define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT	0
154 #define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK	(0xFFF << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT)
155 #define ZYNQMP_CSU_IDCODE_XILINX_ID		0x093
156 
157 #define ZYNQMP_CSU_IDCODE_SVD_SHIFT		12
158 #define ZYNQMP_CSU_IDCODE_SVD_MASK		(0xE << ZYNQMP_CSU_IDCODE_SVD_SHIFT)
159 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT	15
160 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK	(0xF << ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
161 #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT	19
162 #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK	(0x3 << ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT)
163 #define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT		21
164 #define ZYNQMP_CSU_IDCODE_FAMILY_MASK		(0x7F << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT)
165 #define ZYNQMP_CSU_IDCODE_FAMILY		0x23
166 
167 #define ZYNQMP_CSU_IDCODE_REVISION_SHIFT	28
168 #define ZYNQMP_CSU_IDCODE_REVISION_MASK		(0xF << ZYNQMP_CSU_IDCODE_REVISION_SHIFT)
169 #define ZYNQMP_CSU_IDCODE_REVISION		0
170 
171 #define ZYNQMP_CSU_VERSION_OFFSET	0x44
172 
173 /* Access control register defines */
174 #define ACTLR_EL3_L2ACTLR_BIT	(1 << 6)
175 #define ACTLR_EL3_CPUACTLR_BIT	(1 << 0)
176 
177 #endif /* __ZYNQMP_DEF_H__ */
178