1 /*
2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch.h>
8 #include <arm_def.h>
9 #include <arm_xlat_tables.h>
10 #include <bl_common.h>
11 #include <console.h>
12 #include <plat_arm.h>
13 #include <platform_def.h>
14 #include <sp805.h>
15 #include <utils.h>
16 #include "../../../bl1/bl1_private.h"
17
18 /* Weak definitions may be overridden in specific ARM standard platform */
19 #pragma weak bl1_early_platform_setup
20 #pragma weak bl1_plat_arch_setup
21 #pragma weak bl1_platform_setup
22 #pragma weak bl1_plat_sec_mem_layout
23 #pragma weak bl1_plat_prepare_exit
24
25
26 /* Data structure which holds the extents of the trusted SRAM for BL1*/
27 static meminfo_t bl1_tzram_layout;
28
bl1_plat_sec_mem_layout(void)29 meminfo_t *bl1_plat_sec_mem_layout(void)
30 {
31 return &bl1_tzram_layout;
32 }
33
34 /*******************************************************************************
35 * BL1 specific platform actions shared between ARM standard platforms.
36 ******************************************************************************/
arm_bl1_early_platform_setup(void)37 void arm_bl1_early_platform_setup(void)
38 {
39
40 #if !ARM_DISABLE_TRUSTED_WDOG
41 /* Enable watchdog */
42 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL);
43 #endif
44
45 /* Initialize the console to provide early debug support */
46 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
47 ARM_CONSOLE_BAUDRATE);
48
49 /* Allow BL1 to see the whole Trusted RAM */
50 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
51 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
52
53 #if !LOAD_IMAGE_V2
54 /* Calculate how much RAM BL1 is using and how much remains free */
55 bl1_tzram_layout.free_base = ARM_BL_RAM_BASE;
56 bl1_tzram_layout.free_size = ARM_BL_RAM_SIZE;
57 reserve_mem(&bl1_tzram_layout.free_base,
58 &bl1_tzram_layout.free_size,
59 BL1_RAM_BASE,
60 BL1_RAM_LIMIT - BL1_RAM_BASE);
61 #endif /* LOAD_IMAGE_V2 */
62 }
63
bl1_early_platform_setup(void)64 void bl1_early_platform_setup(void)
65 {
66 arm_bl1_early_platform_setup();
67
68 /*
69 * Initialize Interconnect for this cluster during cold boot.
70 * No need for locks as no other CPU is active.
71 */
72 plat_arm_interconnect_init();
73 /*
74 * Enable Interconnect coherency for the primary CPU's cluster.
75 */
76 plat_arm_interconnect_enter_coherency();
77 }
78
79 /******************************************************************************
80 * Perform the very early platform specific architecture setup shared between
81 * ARM standard platforms. This only does basic initialization. Later
82 * architectural setup (bl1_arch_setup()) does not do anything platform
83 * specific.
84 *****************************************************************************/
arm_bl1_plat_arch_setup(void)85 void arm_bl1_plat_arch_setup(void)
86 {
87 arm_setup_page_tables(bl1_tzram_layout.total_base,
88 bl1_tzram_layout.total_size,
89 BL_CODE_BASE,
90 BL1_CODE_END,
91 BL1_RO_DATA_BASE,
92 BL1_RO_DATA_END
93 #if USE_COHERENT_MEM
94 , BL_COHERENT_RAM_BASE,
95 BL_COHERENT_RAM_END
96 #endif
97 );
98 #ifdef AARCH32
99 enable_mmu_secure(0);
100 #else
101 enable_mmu_el3(0);
102 #endif /* AARCH32 */
103 }
104
bl1_plat_arch_setup(void)105 void bl1_plat_arch_setup(void)
106 {
107 arm_bl1_plat_arch_setup();
108 }
109
110 /*
111 * Perform the platform specific architecture setup shared between
112 * ARM standard platforms.
113 */
arm_bl1_platform_setup(void)114 void arm_bl1_platform_setup(void)
115 {
116 /* Initialise the IO layer and register platform IO devices */
117 plat_arm_io_setup();
118 }
119
bl1_platform_setup(void)120 void bl1_platform_setup(void)
121 {
122 arm_bl1_platform_setup();
123 }
124
bl1_plat_prepare_exit(entry_point_info_t * ep_info)125 void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
126 {
127 #if !ARM_DISABLE_TRUSTED_WDOG
128 /* Disable watchdog before leaving BL1 */
129 sp805_stop(ARM_SP805_TWDG_BASE);
130 #endif
131
132 #ifdef EL3_PAYLOAD_BASE
133 /*
134 * Program the EL3 payload's entry point address into the CPUs mailbox
135 * in order to release secondary CPUs from their holding pen and make
136 * them jump there.
137 */
138 arm_program_trusted_mailbox(ep_info->pc);
139 dsbsy();
140 sev();
141 #endif
142 }
143