1 /*
2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_helpers.h>
8 #include <arm_def.h>
9 #include <assert.h>
10 #include <bl_common.h>
11 #include <console.h>
12 #include <debug.h>
13 #include <desc_image_load.h>
14 #include <generic_delay_timer.h>
15 #ifdef SPD_opteed
16 #include <optee_utils.h>
17 #endif
18 #include <plat_arm.h>
19 #include <platform.h>
20 #include <platform_def.h>
21 #include <string.h>
22 #include <utils.h>
23
24 /* Data structure which holds the extents of the trusted SRAM for BL2 */
25 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
26
27 /* Weak definitions may be overridden in specific ARM standard platform */
28 #pragma weak bl2_early_platform_setup
29 #pragma weak bl2_platform_setup
30 #pragma weak bl2_plat_arch_setup
31 #pragma weak bl2_plat_sec_mem_layout
32
33 #if LOAD_IMAGE_V2
34
35 #pragma weak bl2_plat_handle_post_image_load
36
37 #else /* LOAD_IMAGE_V2 */
38
39 /*******************************************************************************
40 * This structure represents the superset of information that is passed to
41 * BL31, e.g. while passing control to it from BL2, bl31_params
42 * and other platform specific params
43 ******************************************************************************/
44 typedef struct bl2_to_bl31_params_mem {
45 bl31_params_t bl31_params;
46 image_info_t bl31_image_info;
47 image_info_t bl32_image_info;
48 image_info_t bl33_image_info;
49 entry_point_info_t bl33_ep_info;
50 entry_point_info_t bl32_ep_info;
51 entry_point_info_t bl31_ep_info;
52 } bl2_to_bl31_params_mem_t;
53
54
55 static bl2_to_bl31_params_mem_t bl31_params_mem;
56
57
58 /* Weak definitions may be overridden in specific ARM standard platform */
59 #pragma weak bl2_plat_get_bl31_params
60 #pragma weak bl2_plat_get_bl31_ep_info
61 #pragma weak bl2_plat_flush_bl31_params
62 #pragma weak bl2_plat_set_bl31_ep_info
63 #pragma weak bl2_plat_get_scp_bl2_meminfo
64 #pragma weak bl2_plat_get_bl32_meminfo
65 #pragma weak bl2_plat_set_bl32_ep_info
66 #pragma weak bl2_plat_get_bl33_meminfo
67 #pragma weak bl2_plat_set_bl33_ep_info
68
69 #if ARM_BL31_IN_DRAM
bl2_plat_sec_mem_layout(void)70 meminfo_t *bl2_plat_sec_mem_layout(void)
71 {
72 static meminfo_t bl2_dram_layout
73 __aligned(CACHE_WRITEBACK_GRANULE) = {
74 .total_base = BL31_BASE,
75 .total_size = (ARM_AP_TZC_DRAM1_BASE +
76 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE,
77 .free_base = BL31_BASE,
78 .free_size = (ARM_AP_TZC_DRAM1_BASE +
79 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE
80 };
81
82 return &bl2_dram_layout;
83 }
84 #else
bl2_plat_sec_mem_layout(void)85 meminfo_t *bl2_plat_sec_mem_layout(void)
86 {
87 return &bl2_tzram_layout;
88 }
89 #endif /* ARM_BL31_IN_DRAM */
90
91 /*******************************************************************************
92 * This function assigns a pointer to the memory that the platform has kept
93 * aside to pass platform specific and trusted firmware related information
94 * to BL31. This memory is allocated by allocating memory to
95 * bl2_to_bl31_params_mem_t structure which is a superset of all the
96 * structure whose information is passed to BL31
97 * NOTE: This function should be called only once and should be done
98 * before generating params to BL31
99 ******************************************************************************/
bl2_plat_get_bl31_params(void)100 bl31_params_t *bl2_plat_get_bl31_params(void)
101 {
102 bl31_params_t *bl2_to_bl31_params;
103
104 /*
105 * Initialise the memory for all the arguments that needs to
106 * be passed to BL31
107 */
108 zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t));
109
110 /* Assign memory for TF related information */
111 bl2_to_bl31_params = &bl31_params_mem.bl31_params;
112 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
113
114 /* Fill BL31 related information */
115 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
116 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
117 VERSION_1, 0);
118
119 /* Fill BL32 related information if it exists */
120 #ifdef BL32_BASE
121 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
122 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
123 VERSION_1, 0);
124 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
125 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
126 VERSION_1, 0);
127 #endif /* BL32_BASE */
128
129 /* Fill BL33 related information */
130 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
131 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
132 PARAM_EP, VERSION_1, 0);
133
134 /* BL33 expects to receive the primary CPU MPID (through x0) */
135 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
136
137 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
138 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
139 VERSION_1, 0);
140
141 return bl2_to_bl31_params;
142 }
143
144 /* Flush the TF params and the TF plat params */
bl2_plat_flush_bl31_params(void)145 void bl2_plat_flush_bl31_params(void)
146 {
147 flush_dcache_range((unsigned long)&bl31_params_mem,
148 sizeof(bl2_to_bl31_params_mem_t));
149 }
150
151 /*******************************************************************************
152 * This function returns a pointer to the shared memory that the platform
153 * has kept to point to entry point information of BL31 to BL2
154 ******************************************************************************/
bl2_plat_get_bl31_ep_info(void)155 struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
156 {
157 #if DEBUG
158 bl31_params_mem.bl31_ep_info.args.arg1 = ARM_BL31_PLAT_PARAM_VAL;
159 #endif
160
161 return &bl31_params_mem.bl31_ep_info;
162 }
163 #endif /* LOAD_IMAGE_V2 */
164
165 /*******************************************************************************
166 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
167 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
168 * Copy it to a safe location before its reclaimed by later BL2 functionality.
169 ******************************************************************************/
arm_bl2_early_platform_setup(meminfo_t * mem_layout)170 void arm_bl2_early_platform_setup(meminfo_t *mem_layout)
171 {
172 /* Initialize the console to provide early debug support */
173 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
174 ARM_CONSOLE_BAUDRATE);
175
176 /* Setup the BL2 memory layout */
177 bl2_tzram_layout = *mem_layout;
178
179 /* Initialise the IO layer and register platform IO devices */
180 plat_arm_io_setup();
181 }
182
bl2_early_platform_setup(meminfo_t * mem_layout)183 void bl2_early_platform_setup(meminfo_t *mem_layout)
184 {
185 arm_bl2_early_platform_setup(mem_layout);
186 generic_delay_timer_init();
187 }
188
189 /*
190 * Perform ARM standard platform setup.
191 */
arm_bl2_platform_setup(void)192 void arm_bl2_platform_setup(void)
193 {
194 /* Initialize the secure environment */
195 plat_arm_security_setup();
196
197 #if defined(PLAT_ARM_MEM_PROT_ADDR)
198 arm_nor_psci_do_mem_protect();
199 #endif
200 }
201
bl2_platform_setup(void)202 void bl2_platform_setup(void)
203 {
204 arm_bl2_platform_setup();
205 }
206
207 /*******************************************************************************
208 * Perform the very early platform specific architectural setup here. At the
209 * moment this is only initializes the mmu in a quick and dirty way.
210 ******************************************************************************/
arm_bl2_plat_arch_setup(void)211 void arm_bl2_plat_arch_setup(void)
212 {
213 arm_setup_page_tables(bl2_tzram_layout.total_base,
214 bl2_tzram_layout.total_size,
215 BL_CODE_BASE,
216 BL_CODE_END,
217 BL_RO_DATA_BASE,
218 BL_RO_DATA_END
219 #if USE_COHERENT_MEM
220 , BL_COHERENT_RAM_BASE,
221 BL_COHERENT_RAM_END
222 #endif
223 );
224
225 #ifdef AARCH32
226 enable_mmu_secure(0);
227 #else
228 enable_mmu_el1(0);
229 #endif
230 }
231
bl2_plat_arch_setup(void)232 void bl2_plat_arch_setup(void)
233 {
234 arm_bl2_plat_arch_setup();
235 }
236
237 #if LOAD_IMAGE_V2
arm_bl2_handle_post_image_load(unsigned int image_id)238 int arm_bl2_handle_post_image_load(unsigned int image_id)
239 {
240 int err = 0;
241 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
242 #ifdef SPD_opteed
243 bl_mem_params_node_t *pager_mem_params = NULL;
244 bl_mem_params_node_t *paged_mem_params = NULL;
245 #endif
246 assert(bl_mem_params);
247
248 switch (image_id) {
249 #ifdef AARCH64
250 case BL32_IMAGE_ID:
251 #ifdef SPD_opteed
252 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
253 assert(pager_mem_params);
254
255 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
256 assert(paged_mem_params);
257
258 err = parse_optee_header(&bl_mem_params->ep_info,
259 &pager_mem_params->image_info,
260 &paged_mem_params->image_info);
261 if (err != 0) {
262 WARN("OPTEE header parse error.\n");
263 }
264 #endif
265 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry();
266 break;
267 #endif
268
269 case BL33_IMAGE_ID:
270 /* BL33 expects to receive the primary CPU MPID (through r0) */
271 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
272 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry();
273 break;
274
275 #ifdef SCP_BL2_BASE
276 case SCP_BL2_IMAGE_ID:
277 /* The subsequent handling of SCP_BL2 is platform specific */
278 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info);
279 if (err) {
280 WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
281 }
282 break;
283 #endif
284 }
285
286 return err;
287 }
288
289 /*******************************************************************************
290 * This function can be used by the platforms to update/use image
291 * information for given `image_id`.
292 ******************************************************************************/
bl2_plat_handle_post_image_load(unsigned int image_id)293 int bl2_plat_handle_post_image_load(unsigned int image_id)
294 {
295 return arm_bl2_handle_post_image_load(image_id);
296 }
297
298 #else /* LOAD_IMAGE_V2 */
299
300 /*******************************************************************************
301 * Populate the extents of memory available for loading SCP_BL2 (if used),
302 * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2.
303 ******************************************************************************/
bl2_plat_get_scp_bl2_meminfo(meminfo_t * scp_bl2_meminfo)304 void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)
305 {
306 *scp_bl2_meminfo = bl2_tzram_layout;
307 }
308
309 /*******************************************************************************
310 * Before calling this function BL31 is loaded in memory and its entrypoint
311 * is set by load_image. This is a placeholder for the platform to change
312 * the entrypoint of BL31 and set SPSR and security state.
313 * On ARM standard platforms we only set the security state of the entrypoint
314 ******************************************************************************/
bl2_plat_set_bl31_ep_info(image_info_t * bl31_image_info,entry_point_info_t * bl31_ep_info)315 void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
316 entry_point_info_t *bl31_ep_info)
317 {
318 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
319 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
320 DISABLE_ALL_EXCEPTIONS);
321 }
322
323
324 /*******************************************************************************
325 * Before calling this function BL32 is loaded in memory and its entrypoint
326 * is set by load_image. This is a placeholder for the platform to change
327 * the entrypoint of BL32 and set SPSR and security state.
328 * On ARM standard platforms we only set the security state of the entrypoint
329 ******************************************************************************/
330 #ifdef BL32_BASE
bl2_plat_set_bl32_ep_info(image_info_t * bl32_image_info,entry_point_info_t * bl32_ep_info)331 void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
332 entry_point_info_t *bl32_ep_info)
333 {
334 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
335 bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry();
336 }
337
338 /*******************************************************************************
339 * Populate the extents of memory available for loading BL32
340 ******************************************************************************/
bl2_plat_get_bl32_meminfo(meminfo_t * bl32_meminfo)341 void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
342 {
343 /*
344 * Populate the extents of memory available for loading BL32.
345 */
346 bl32_meminfo->total_base = BL32_BASE;
347 bl32_meminfo->free_base = BL32_BASE;
348 bl32_meminfo->total_size =
349 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
350 bl32_meminfo->free_size =
351 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
352 }
353 #endif /* BL32_BASE */
354
355 /*******************************************************************************
356 * Before calling this function BL33 is loaded in memory and its entrypoint
357 * is set by load_image. This is a placeholder for the platform to change
358 * the entrypoint of BL33 and set SPSR and security state.
359 * On ARM standard platforms we only set the security state of the entrypoint
360 ******************************************************************************/
bl2_plat_set_bl33_ep_info(image_info_t * image,entry_point_info_t * bl33_ep_info)361 void bl2_plat_set_bl33_ep_info(image_info_t *image,
362 entry_point_info_t *bl33_ep_info)
363 {
364 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
365 bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry();
366 }
367
368 /*******************************************************************************
369 * Populate the extents of memory available for loading BL33
370 ******************************************************************************/
bl2_plat_get_bl33_meminfo(meminfo_t * bl33_meminfo)371 void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
372 {
373 bl33_meminfo->total_base = ARM_NS_DRAM1_BASE;
374 bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE;
375 bl33_meminfo->free_base = ARM_NS_DRAM1_BASE;
376 bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE;
377 }
378
379 #endif /* LOAD_IMAGE_V2 */
380