1 /*
2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch.h>
8 #include <arch_helpers.h>
9 #include <assert.h>
10 #include <bl31.h>
11 #include <bl_common.h>
12 #include <console.h>
13 #include <cortex_a53.h>
14 #include <cortex_a57.h>
15 #include <debug.h>
16 #include <denver.h>
17 #include <errno.h>
18 #include <memctrl.h>
19 #include <mmio.h>
20 #include <platform.h>
21 #include <platform_def.h>
22 #include <stddef.h>
23 #include <string.h>
24 #include <tegra_def.h>
25 #include <tegra_private.h>
26
27 extern void zeromem16(void *mem, unsigned int length);
28
29 /*******************************************************************************
30 * Declarations of linker defined symbols which will help us find the layout
31 * of trusted SRAM
32 ******************************************************************************/
33 extern unsigned long __TEXT_START__;
34 extern unsigned long __TEXT_END__;
35 extern unsigned long __RW_START__;
36 extern unsigned long __RW_END__;
37 extern unsigned long __RODATA_START__;
38 extern unsigned long __RODATA_END__;
39 extern unsigned long __BL31_END__;
40
41 extern uint64_t tegra_bl31_phys_base;
42 extern uint64_t tegra_console_base;
43
44 /*
45 * The next 3 constants identify the extents of the code, RO data region and the
46 * limit of the BL3-1 image. These addresses are used by the MMU setup code and
47 * therefore they must be page-aligned. It is the responsibility of the linker
48 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
49 * refer to page-aligned addresses.
50 */
51 #define BL31_RW_START (unsigned long)(&__RW_START__)
52 #define BL31_RW_END (unsigned long)(&__RW_END__)
53 #define BL31_RODATA_BASE (unsigned long)(&__RODATA_START__)
54 #define BL31_RODATA_END (unsigned long)(&__RODATA_END__)
55 #define BL31_END (unsigned long)(&__BL31_END__)
56
57 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
58 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
59 .tzdram_size = (uint64_t)TZDRAM_SIZE
60 };
61
62 /*******************************************************************************
63 * This variable holds the non-secure image entry address
64 ******************************************************************************/
65 extern uint64_t ns_image_entrypoint;
66
67 /*******************************************************************************
68 * The following platform setup functions are weakly defined. They
69 * provide typical implementations that will be overridden by a SoC.
70 ******************************************************************************/
71 #pragma weak plat_early_platform_setup
72 #pragma weak plat_get_bl31_params
73 #pragma weak plat_get_bl31_plat_params
74
plat_early_platform_setup(void)75 void plat_early_platform_setup(void)
76 {
77 ; /* do nothing */
78 }
79
plat_get_bl31_params(void)80 bl31_params_t *plat_get_bl31_params(void)
81 {
82 return NULL;
83 }
84
plat_get_bl31_plat_params(void)85 plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
86 {
87 return NULL;
88 }
89
90 /*******************************************************************************
91 * Return a pointer to the 'entry_point_info' structure of the next image for
92 * security state specified. BL33 corresponds to the non-secure image type
93 * while BL32 corresponds to the secure image type.
94 ******************************************************************************/
bl31_plat_get_next_image_ep_info(uint32_t type)95 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
96 {
97 if (type == NON_SECURE)
98 return &bl33_image_ep_info;
99
100 /* return BL32 entry point info if it is valid */
101 if (type == SECURE && bl32_image_ep_info.pc)
102 return &bl32_image_ep_info;
103
104 return NULL;
105 }
106
107 /*******************************************************************************
108 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image
109 * passes this platform specific information.
110 ******************************************************************************/
bl31_get_plat_params(void)111 plat_params_from_bl2_t *bl31_get_plat_params(void)
112 {
113 return &plat_bl31_params_from_bl2;
114 }
115
116 /*******************************************************************************
117 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image
118 * info.
119 ******************************************************************************/
bl31_early_platform_setup(bl31_params_t * from_bl2,void * plat_params_from_bl2)120 void bl31_early_platform_setup(bl31_params_t *from_bl2,
121 void *plat_params_from_bl2)
122 {
123 plat_params_from_bl2_t *plat_params =
124 (plat_params_from_bl2_t *)plat_params_from_bl2;
125 #if LOG_LEVEL >= LOG_LEVEL_INFO
126 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
127 #endif
128 image_info_t bl32_img_info = { {0} };
129 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
130
131 /*
132 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
133 * there's no argument to relay from a previous bootloader. Platforms
134 * might use custom ways to get arguments, so provide handlers which
135 * they can override.
136 */
137 if (from_bl2 == NULL)
138 from_bl2 = plat_get_bl31_params();
139 if (plat_params == NULL)
140 plat_params = plat_get_bl31_plat_params();
141
142 /*
143 * Copy BL3-3, BL3-2 entry point information.
144 * They are stored in Secure RAM, in BL2's address space.
145 */
146 assert(from_bl2);
147 assert(from_bl2->bl33_ep_info);
148 bl33_image_ep_info = *from_bl2->bl33_ep_info;
149
150 if (from_bl2->bl32_ep_info)
151 bl32_image_ep_info = *from_bl2->bl32_ep_info;
152
153 /*
154 * Parse platform specific parameters - TZDRAM aperture base and size
155 */
156 assert(plat_params);
157 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
158 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
159 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
160
161 /*
162 * It is very important that we run either from TZDRAM or TZSRAM base.
163 * Add an explicit check here.
164 */
165 if ((plat_bl31_params_from_bl2.tzdram_base != BL31_BASE) &&
166 (TEGRA_TZRAM_BASE != BL31_BASE))
167 panic();
168
169 /*
170 * Get the base address of the UART controller to be used for the
171 * console
172 */
173 tegra_console_base = plat_get_console_from_id(plat_params->uart_id);
174
175 if (tegra_console_base != (uint64_t)0) {
176 /*
177 * Configure the UART port to be used as the console
178 */
179 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ,
180 TEGRA_CONSOLE_BAUDRATE);
181 }
182
183 /*
184 * Initialize delay timer
185 */
186 tegra_delay_timer_init();
187
188 /*
189 * Do initial security configuration to allow DRAM/device access.
190 */
191 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base,
192 plat_bl31_params_from_bl2.tzdram_size);
193
194 /*
195 * The previous bootloader might not have placed the BL32 image
196 * inside the TZDRAM. We check the BL32 image info to find out
197 * the base/PC values and relocate the image if necessary.
198 */
199 if (from_bl2->bl32_image_info) {
200
201 bl32_img_info = *from_bl2->bl32_image_info;
202
203 /* Relocate BL32 if it resides outside of the TZDRAM */
204 tzdram_start = plat_bl31_params_from_bl2.tzdram_base;
205 tzdram_end = plat_bl31_params_from_bl2.tzdram_base +
206 plat_bl31_params_from_bl2.tzdram_size;
207 bl32_start = bl32_img_info.image_base;
208 bl32_end = bl32_img_info.image_base + bl32_img_info.image_size;
209
210 assert(tzdram_end > tzdram_start);
211 assert(bl32_end > bl32_start);
212 assert(bl32_image_ep_info.pc > tzdram_start);
213 assert(bl32_image_ep_info.pc < tzdram_end);
214
215 /* relocate BL32 */
216 if (bl32_start >= tzdram_end || bl32_end <= tzdram_start) {
217
218 INFO("Relocate BL32 to TZDRAM\n");
219
220 memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc,
221 (void *)(uintptr_t)bl32_start,
222 bl32_img_info.image_size);
223
224 /* clean up non-secure intermediate buffer */
225 zeromem16((void *)(uintptr_t)bl32_start,
226 bl32_img_info.image_size);
227 }
228 }
229
230 /* Early platform setup for Tegra SoCs */
231 plat_early_platform_setup();
232
233 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ?
234 "Denver" : "ARM", read_mpidr());
235 }
236
237 /*******************************************************************************
238 * Initialize the gic, configure the SCR.
239 ******************************************************************************/
bl31_platform_setup(void)240 void bl31_platform_setup(void)
241 {
242 uint32_t tmp_reg;
243
244 /* Initialize the gic cpu and distributor interfaces */
245 plat_gic_setup();
246
247 /*
248 * Setup secondary CPU POR infrastructure.
249 */
250 plat_secondary_setup();
251
252 /*
253 * Initial Memory Controller configuration.
254 */
255 tegra_memctrl_setup();
256
257 /*
258 * Set up the TZRAM memory aperture to allow only secure world
259 * access
260 */
261 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE);
262
263 /* Set the next EL to be AArch64 */
264 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT;
265 write_scr(tmp_reg);
266
267 INFO("BL3-1: Tegra platform setup complete\n");
268 }
269
270 /*******************************************************************************
271 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit
272 ******************************************************************************/
bl31_plat_runtime_setup(void)273 void bl31_plat_runtime_setup(void)
274 {
275 /*
276 * During boot, USB3 and flash media (SDMMC/SATA) devices need
277 * access to IRAM. Because these clients connect to the MC and
278 * do not have a direct path to the IRAM, the MC implements AHB
279 * redirection during boot to allow path to IRAM. In this mode
280 * accesses to a programmed memory address aperture are directed
281 * to the AHB bus, allowing access to the IRAM. This mode must be
282 * disabled before we jump to the non-secure world.
283 */
284 tegra_memctrl_disable_ahb_redirection();
285 }
286
287 /*******************************************************************************
288 * Perform the very early platform specific architectural setup here. At the
289 * moment this only intializes the mmu in a quick and dirty way.
290 ******************************************************************************/
bl31_plat_arch_setup(void)291 void bl31_plat_arch_setup(void)
292 {
293 unsigned long rw_start = BL31_RW_START;
294 unsigned long rw_size = BL31_RW_END - BL31_RW_START;
295 unsigned long rodata_start = BL31_RODATA_BASE;
296 unsigned long rodata_size = BL31_RODATA_END - BL31_RODATA_BASE;
297 unsigned long code_base = (unsigned long)(&__TEXT_START__);
298 unsigned long code_size = (unsigned long)(&__TEXT_END__) - code_base;
299 const mmap_region_t *plat_mmio_map = NULL;
300 #if USE_COHERENT_MEM
301 unsigned long coh_start, coh_size;
302 #endif
303 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
304
305 /* add memory regions */
306 mmap_add_region(rw_start, rw_start,
307 rw_size,
308 MT_MEMORY | MT_RW | MT_SECURE);
309 mmap_add_region(rodata_start, rodata_start,
310 rodata_size,
311 MT_RO_DATA | MT_SECURE);
312 mmap_add_region(code_base, code_base,
313 code_size,
314 MT_CODE | MT_SECURE);
315
316 /* map TZDRAM used by BL31 as coherent memory */
317 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
318 mmap_add_region(params_from_bl2->tzdram_base,
319 params_from_bl2->tzdram_base,
320 BL31_SIZE,
321 MT_DEVICE | MT_RW | MT_SECURE);
322 }
323
324 #if USE_COHERENT_MEM
325 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE);
326 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE;
327
328 mmap_add_region(coh_start, coh_start,
329 coh_size,
330 MT_DEVICE | MT_RW | MT_SECURE);
331 #endif
332
333 /* map on-chip free running uS timer */
334 mmap_add_region(page_align((uint64_t)TEGRA_TMRUS_BASE, 0),
335 page_align((uint64_t)TEGRA_TMRUS_BASE, 0),
336 (uint64_t)TEGRA_TMRUS_SIZE,
337 MT_DEVICE | MT_RO | MT_SECURE);
338
339 /* add MMIO space */
340 plat_mmio_map = plat_get_mmio_map();
341 if (plat_mmio_map)
342 mmap_add(plat_mmio_map);
343 else
344 WARN("MMIO map not available\n");
345
346 /* set up translation tables */
347 init_xlat_tables();
348
349 /* enable the MMU */
350 enable_mmu_el3(0);
351
352 INFO("BL3-1: Tegra: MMU enabled\n");
353 }
354
355 /*******************************************************************************
356 * Check if the given NS DRAM range is valid
357 ******************************************************************************/
bl31_check_ns_address(uint64_t base,uint64_t size_in_bytes)358 int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
359 {
360 uint64_t end = base + size_in_bytes;
361
362 /*
363 * Check if the NS DRAM address is valid
364 */
365 if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END)) {
366 ERROR("NS address is out-of-bounds!\n");
367 return -EFAULT;
368 }
369
370 /*
371 * TZDRAM aperture contains the BL31 and BL32 images, so we need
372 * to check if the NS DRAM range overlaps the TZDRAM aperture.
373 */
374 if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) {
375 ERROR("NS address overlaps TZDRAM!\n");
376 return -ENOTSUP;
377 }
378
379 /* valid NS address */
380 return 0;
381 }
382