1/*
2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <bl_common.h>
10#include <cortex_a53.h>
11#include <cortex_a72.h>
12#include <plat_private.h>
13#include <platform_def.h>
14#include <plat_pmu_macros.S>
15
16	.globl	cpuson_entry_point
17	.globl	cpuson_flags
18	.globl	platform_cpu_warmboot
19	.globl	plat_secondary_cold_boot_setup
20	.globl	plat_report_exception
21	.globl	platform_is_primary_cpu
22	.globl	plat_crash_console_init
23	.globl	plat_crash_console_putc
24	.globl	plat_my_core_pos
25	.globl	plat_reset_handler
26
27	/*
28	 * void plat_reset_handler(void);
29	 *
30	 * Determine the SOC type and call the appropriate reset
31	 * handler.
32	 *
33	 */
34func plat_reset_handler
35	mrs x0, midr_el1
36	ubfx x0, x0, MIDR_PN_SHIFT, #12
37	cmp w0, #((CORTEX_A72_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
38	b.eq	handler_a72
39	b	handler_end
40handler_a72:
41	/*
42	 * This handler does the following:
43	 * Set the L2 Data RAM latency for Cortex-A72.
44	 * Set the L2 Tag RAM latency to for Cortex-A72.
45	 */
46	mov x0, #((5 << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) |	\
47			 (0x1 << 5))
48	msr	CORTEX_A72_L2CTLR_EL1, x0
49	isb
50handler_end:
51	ret
52endfunc plat_reset_handler
53
54func plat_my_core_pos
55	mrs	x0, mpidr_el1
56	and	x1, x0, #MPIDR_CPU_MASK
57	and	x0, x0, #MPIDR_CLUSTER_MASK
58	add	x0, x1, x0, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT
59	ret
60endfunc plat_my_core_pos
61
62	/* --------------------------------------------------------------------
63	 * void plat_secondary_cold_boot_setup (void);
64	 *
65	 * This function performs any platform specific actions
66	 * needed for a secondary cpu after a cold reset e.g
67	 * mark the cpu's presence, mechanism to place it in a
68	 * holding pen etc.
69	 * --------------------------------------------------------------------
70	 */
71func plat_secondary_cold_boot_setup
72	/* rk3368 does not do cold boot for secondary CPU */
73cb_panic:
74	b	cb_panic
75endfunc plat_secondary_cold_boot_setup
76
77func platform_is_primary_cpu
78	and	x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
79	cmp	x0, #PLAT_RK_PRIMARY_CPU
80	cset	x0, eq
81	ret
82endfunc platform_is_primary_cpu
83
84	/* --------------------------------------------------------------------
85	 * int plat_crash_console_init(void)
86	 * Function to initialize the crash console
87	 * without a C Runtime to print crash report.
88	 * Clobber list : x0, x1, x2
89	 * --------------------------------------------------------------------
90	 */
91func plat_crash_console_init
92	mov_imm	x0, PLAT_RK_UART_BASE
93	mov_imm	x1, PLAT_RK_UART_CLOCK
94	mov_imm	x2, PLAT_RK_UART_BAUDRATE
95	b	console_core_init
96endfunc plat_crash_console_init
97
98	/* --------------------------------------------------------------------
99	 * int plat_crash_console_putc(void)
100	 * Function to print a character on the crash
101	 * console without a C Runtime.
102	 * Clobber list : x1, x2
103	 * --------------------------------------------------------------------
104	 */
105func plat_crash_console_putc
106	mov_imm x1, PLAT_RK_UART_BASE
107	b	console_core_putc
108endfunc plat_crash_console_putc
109
110	/* --------------------------------------------------------------------
111	 * void platform_cpu_warmboot (void);
112	 * cpus online or resume enterpoint
113	 * --------------------------------------------------------------------
114	 */
115func platform_cpu_warmboot _align=16
116	mrs	x0, MPIDR_EL1
117	and	x19, x0, #MPIDR_CPU_MASK
118	and	x20, x0, #MPIDR_CLUSTER_MASK
119	mov	x0, x20
120	func_rockchip_clst_warmboot
121	/* --------------------------------------------------------------------
122	 * big cluster id is 1
123	 * big cores id is from 0-3, little cores id 4-7
124	 * --------------------------------------------------------------------
125	 */
126	add	x21, x19, x20, lsr #PLAT_RK_CLST_TO_CPUID_SHIFT
127	/* --------------------------------------------------------------------
128	 * get per cpuup flag
129         * --------------------------------------------------------------------
130	 */
131	adr	x4, cpuson_flags
132	add	x4, x4, x21, lsl #2
133	ldr	w1, [x4]
134	/* --------------------------------------------------------------------
135	 * check cpuon reason
136         * --------------------------------------------------------------------
137	 */
138	cmp	w1, PMU_CPU_AUTO_PWRDN
139	b.eq	boot_entry
140	cmp	w1, PMU_CPU_HOTPLUG
141	b.eq	boot_entry
142	/* --------------------------------------------------------------------
143	 * If the boot core cpuson_flags or cpuson_entry_point is not
144	 * expection. force the core into wfe.
145         * --------------------------------------------------------------------
146	 */
147wfe_loop:
148	wfe
149	b	wfe_loop
150boot_entry:
151	str	wzr, [x4]
152	/* --------------------------------------------------------------------
153	 * get per cpuup boot addr
154	 * --------------------------------------------------------------------
155	 */
156	adr	x5, cpuson_entry_point
157	ldr	x2, [x5, x21, lsl #3]
158	br	x2
159endfunc platform_cpu_warmboot
160
161	/* --------------------------------------------------------------------
162	 * Per-CPU Secure entry point - resume or power up
163	 * --------------------------------------------------------------------
164	 */
165	.section tzfw_coherent_mem, "a"
166	.align  3
167cpuson_entry_point:
168	.rept	PLATFORM_CORE_COUNT
169	.quad	0
170	.endr
171cpuson_flags:
172	.rept	PLATFORM_CORE_COUNT
173	.word	0
174	.endr
175rockchip_clst_warmboot_data
176