1/*
2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <context.h>
10#include <cpu_data.h>
11#include <interrupt_mgmt.h>
12#include <platform_def.h>
13#include <runtime_svc.h>
14
15	.globl	runtime_exceptions
16
17	/* ---------------------------------------------------------------------
18	 * This macro handles Synchronous exceptions.
19	 * Only SMC exceptions are supported.
20	 * ---------------------------------------------------------------------
21	 */
22	.macro	handle_sync_exception
23	/* Enable the SError interrupt */
24	msr	daifclr, #DAIF_ABT_BIT
25
26	str	x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
27
28#if ENABLE_RUNTIME_INSTRUMENTATION
29	/*
30	 * Read the timestamp value and store it in per-cpu data. The value
31	 * will be extracted from per-cpu data by the C level SMC handler and
32	 * saved to the PMF timestamp region.
33	 */
34	mrs	x30, cntpct_el0
35	str	x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
36	mrs	x29, tpidr_el3
37	str	x30, [x29, #CPU_DATA_PMF_TS0_OFFSET]
38	ldr	x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
39#endif
40
41	mrs	x30, esr_el3
42	ubfx	x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
43
44	/* Handle SMC exceptions separately from other synchronous exceptions */
45	cmp	x30, #EC_AARCH32_SMC
46	b.eq	smc_handler32
47
48	cmp	x30, #EC_AARCH64_SMC
49	b.eq	smc_handler64
50
51	/* Other kinds of synchronous exceptions are not handled */
52	ldr	x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
53	b	report_unhandled_exception
54	.endm
55
56
57	/* ---------------------------------------------------------------------
58	 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS
59	 * interrupts.
60	 * ---------------------------------------------------------------------
61	 */
62	.macro	handle_interrupt_exception label
63	/* Enable the SError interrupt */
64	msr	daifclr, #DAIF_ABT_BIT
65
66	str	x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
67	bl	save_gp_registers
68
69	/* Save the EL3 system registers needed to return from this exception */
70	mrs	x0, spsr_el3
71	mrs	x1, elr_el3
72	stp	x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
73
74	/* Switch to the runtime stack i.e. SP_EL0 */
75	ldr	x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
76	mov	x20, sp
77	msr	spsel, #0
78	mov	sp, x2
79
80	/*
81	 * Find out whether this is a valid interrupt type.
82	 * If the interrupt controller reports a spurious interrupt then return
83	 * to where we came from.
84	 */
85	bl	plat_ic_get_pending_interrupt_type
86	cmp	x0, #INTR_TYPE_INVAL
87	b.eq	interrupt_exit_\label
88
89	/*
90	 * Get the registered handler for this interrupt type.
91	 * A NULL return value could be 'cause of the following conditions:
92	 *
93	 * a. An interrupt of a type was routed correctly but a handler for its
94	 *    type was not registered.
95	 *
96	 * b. An interrupt of a type was not routed correctly so a handler for
97	 *    its type was not registered.
98	 *
99	 * c. An interrupt of a type was routed correctly to EL3, but was
100	 *    deasserted before its pending state could be read. Another
101	 *    interrupt of a different type pended at the same time and its
102	 *    type was reported as pending instead. However, a handler for this
103	 *    type was not registered.
104	 *
105	 * a. and b. can only happen due to a programming error. The
106	 * occurrence of c. could be beyond the control of Trusted Firmware.
107	 * It makes sense to return from this exception instead of reporting an
108	 * error.
109	 */
110	bl	get_interrupt_type_handler
111	cbz	x0, interrupt_exit_\label
112	mov	x21, x0
113
114	mov	x0, #INTR_ID_UNAVAILABLE
115
116	/* Set the current security state in the 'flags' parameter */
117	mrs	x2, scr_el3
118	ubfx	x1, x2, #0, #1
119
120	/* Restore the reference to the 'handle' i.e. SP_EL3 */
121	mov	x2, x20
122
123	/* x3 will point to a cookie (not used now) */
124	mov	x3, xzr
125
126	/* Call the interrupt type handler */
127	blr	x21
128
129interrupt_exit_\label:
130	/* Return from exception, possibly in a different security state */
131	b	el3_exit
132
133	.endm
134
135
136	.macro save_x18_to_x29_sp_el0
137	stp	x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
138	stp	x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
139	stp	x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
140	stp	x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
141	stp	x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
142	stp	x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
143	mrs	x18, sp_el0
144	str	x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
145	.endm
146
147
148vector_base runtime_exceptions
149
150	/* ---------------------------------------------------------------------
151	 * Current EL with SP_EL0 : 0x0 - 0x200
152	 * ---------------------------------------------------------------------
153	 */
154vector_entry sync_exception_sp_el0
155	/* We don't expect any synchronous exceptions from EL3 */
156	b	report_unhandled_exception
157	check_vector_size sync_exception_sp_el0
158
159vector_entry irq_sp_el0
160	/*
161	 * EL3 code is non-reentrant. Any asynchronous exception is a serious
162	 * error. Loop infinitely.
163	 */
164	b	report_unhandled_interrupt
165	check_vector_size irq_sp_el0
166
167
168vector_entry fiq_sp_el0
169	b	report_unhandled_interrupt
170	check_vector_size fiq_sp_el0
171
172
173vector_entry serror_sp_el0
174	b	report_unhandled_exception
175	check_vector_size serror_sp_el0
176
177	/* ---------------------------------------------------------------------
178	 * Current EL with SP_ELx: 0x200 - 0x400
179	 * ---------------------------------------------------------------------
180	 */
181vector_entry sync_exception_sp_elx
182	/*
183	 * This exception will trigger if anything went wrong during a previous
184	 * exception entry or exit or while handling an earlier unexpected
185	 * synchronous exception. There is a high probability that SP_EL3 is
186	 * corrupted.
187	 */
188	b	report_unhandled_exception
189	check_vector_size sync_exception_sp_elx
190
191vector_entry irq_sp_elx
192	b	report_unhandled_interrupt
193	check_vector_size irq_sp_elx
194
195vector_entry fiq_sp_elx
196	b	report_unhandled_interrupt
197	check_vector_size fiq_sp_elx
198
199vector_entry serror_sp_elx
200	b	report_unhandled_exception
201	check_vector_size serror_sp_elx
202
203	/* ---------------------------------------------------------------------
204	 * Lower EL using AArch64 : 0x400 - 0x600
205	 * ---------------------------------------------------------------------
206	 */
207vector_entry sync_exception_aarch64
208	/*
209	 * This exception vector will be the entry point for SMCs and traps
210	 * that are unhandled at lower ELs most commonly. SP_EL3 should point
211	 * to a valid cpu context where the general purpose and system register
212	 * state can be saved.
213	 */
214	handle_sync_exception
215	check_vector_size sync_exception_aarch64
216
217vector_entry irq_aarch64
218	handle_interrupt_exception irq_aarch64
219	check_vector_size irq_aarch64
220
221vector_entry fiq_aarch64
222	handle_interrupt_exception fiq_aarch64
223	check_vector_size fiq_aarch64
224
225vector_entry serror_aarch64
226	/*
227	 * SError exceptions from lower ELs are not currently supported.
228	 * Report their occurrence.
229	 */
230	b	report_unhandled_exception
231	check_vector_size serror_aarch64
232
233	/* ---------------------------------------------------------------------
234	 * Lower EL using AArch32 : 0x600 - 0x800
235	 * ---------------------------------------------------------------------
236	 */
237vector_entry sync_exception_aarch32
238	/*
239	 * This exception vector will be the entry point for SMCs and traps
240	 * that are unhandled at lower ELs most commonly. SP_EL3 should point
241	 * to a valid cpu context where the general purpose and system register
242	 * state can be saved.
243	 */
244	handle_sync_exception
245	check_vector_size sync_exception_aarch32
246
247vector_entry irq_aarch32
248	handle_interrupt_exception irq_aarch32
249	check_vector_size irq_aarch32
250
251vector_entry fiq_aarch32
252	handle_interrupt_exception fiq_aarch32
253	check_vector_size fiq_aarch32
254
255vector_entry serror_aarch32
256	/*
257	 * SError exceptions from lower ELs are not currently supported.
258	 * Report their occurrence.
259	 */
260	b	report_unhandled_exception
261	check_vector_size serror_aarch32
262
263
264	/* ---------------------------------------------------------------------
265	 * The following code handles secure monitor calls.
266	 * Depending upon the execution state from where the SMC has been
267	 * invoked, it frees some general purpose registers to perform the
268	 * remaining tasks. They involve finding the runtime service handler
269	 * that is the target of the SMC & switching to runtime stacks (SP_EL0)
270	 * before calling the handler.
271	 *
272	 * Note that x30 has been explicitly saved and can be used here
273	 * ---------------------------------------------------------------------
274	 */
275func smc_handler
276smc_handler32:
277	/* Check whether aarch32 issued an SMC64 */
278	tbnz	x0, #FUNCID_CC_SHIFT, smc_prohibited
279
280	/*
281	 * Since we're are coming from aarch32, x8-x18 need to be saved as per
282	 * SMC32 calling convention. If a lower EL in aarch64 is making an
283	 * SMC32 call then it must have saved x8-x17 already therein.
284	 */
285	stp	x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
286	stp	x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
287	stp	x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
288	stp	x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
289	stp	x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
290
291	/* x4-x7, x18, sp_el0 are saved below */
292
293smc_handler64:
294	/*
295	 * Populate the parameters for the SMC handler.
296	 * We already have x0-x4 in place. x5 will point to a cookie (not used
297	 * now). x6 will point to the context structure (SP_EL3) and x7 will
298	 * contain flags we need to pass to the handler Hence save x5-x7.
299	 *
300	 * Note: x4 only needs to be preserved for AArch32 callers but we do it
301	 *       for AArch64 callers as well for convenience
302	 */
303	stp	x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
304	stp	x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
305
306	/* Save rest of the gpregs and sp_el0*/
307	save_x18_to_x29_sp_el0
308
309	mov	x5, xzr
310	mov	x6, sp
311
312	/* Get the unique owning entity number */
313	ubfx	x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
314	ubfx	x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
315	orr	x16, x16, x15, lsl #FUNCID_OEN_WIDTH
316
317	adr	x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
318
319	/* Load descriptor index from array of indices */
320	adr	x14, rt_svc_descs_indices
321	ldrb	w15, [x14, x16]
322
323	/*
324	 * Restore the saved C runtime stack value which will become the new
325	 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context'
326	 * structure prior to the last ERET from EL3.
327	 */
328	ldr	x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
329
330	/*
331	 * Any index greater than 127 is invalid. Check bit 7 for
332	 * a valid index
333	 */
334	tbnz	w15, 7, smc_unknown
335
336	/* Switch to SP_EL0 */
337	msr	spsel, #0
338
339	/*
340	 * Get the descriptor using the index
341	 * x11 = (base + off), x15 = index
342	 *
343	 * handler = (base + off) + (index << log2(size))
344	 */
345	lsl	w10, w15, #RT_SVC_SIZE_LOG2
346	ldr	x15, [x11, w10, uxtw]
347
348	/*
349	 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world
350	 * switch during SMC handling.
351	 * TODO: Revisit if all system registers can be saved later.
352	 */
353	mrs	x16, spsr_el3
354	mrs	x17, elr_el3
355	mrs	x18, scr_el3
356	stp	x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
357	str	x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
358
359	/* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
360	bfi	x7, x18, #0, #1
361
362	mov	sp, x12
363
364	/*
365	 * Call the Secure Monitor Call handler and then drop directly into
366	 * el3_exit() which will program any remaining architectural state
367	 * prior to issuing the ERET to the desired lower EL.
368	 */
369#if DEBUG
370	cbz	x15, rt_svc_fw_critical_error
371#endif
372	blr	x15
373
374	b	el3_exit
375
376smc_unknown:
377	/*
378	 * Here we restore x4-x18 regardless of where we came from. AArch32
379	 * callers will find the registers contents unchanged, but AArch64
380	 * callers will find the registers modified (with stale earlier NS
381	 * content). Either way, we aren't leaking any secure information
382	 * through them.
383	 */
384	mov	w0, #SMC_UNK
385	b	restore_gp_registers_callee_eret
386
387smc_prohibited:
388	ldr	x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
389	mov	w0, #SMC_UNK
390	eret
391
392rt_svc_fw_critical_error:
393	/* Switch to SP_ELx */
394	msr	spsel, #1
395	no_ret	report_unhandled_exception
396endfunc smc_handler
397