1/*
2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <bl_common.h>
10#include <tsp.h>
11
12
13	/* ----------------------------------------------------
14	 * The caller-saved registers x0-x18 and LR are saved
15	 * here.
16	 * ----------------------------------------------------
17	 */
18
19#define SCRATCH_REG_SIZE #(20 * 8)
20
21	.macro save_caller_regs_and_lr
22	sub	sp, sp, SCRATCH_REG_SIZE
23	stp	x0, x1, [sp]
24	stp	x2, x3, [sp, #0x10]
25	stp	x4, x5, [sp, #0x20]
26	stp	x6, x7, [sp, #0x30]
27	stp	x8, x9, [sp, #0x40]
28	stp	x10, x11, [sp, #0x50]
29	stp	x12, x13, [sp, #0x60]
30	stp	x14, x15, [sp, #0x70]
31	stp	x16, x17, [sp, #0x80]
32	stp	x18, x30, [sp, #0x90]
33	.endm
34
35	.macro restore_caller_regs_and_lr
36	ldp	x0, x1, [sp]
37	ldp	x2, x3, [sp, #0x10]
38	ldp	x4, x5, [sp, #0x20]
39	ldp	x6, x7, [sp, #0x30]
40	ldp	x8, x9, [sp, #0x40]
41	ldp	x10, x11, [sp, #0x50]
42	ldp	x12, x13, [sp, #0x60]
43	ldp	x14, x15, [sp, #0x70]
44	ldp	x16, x17, [sp, #0x80]
45	ldp	x18, x30, [sp, #0x90]
46	add	sp, sp, SCRATCH_REG_SIZE
47	.endm
48
49	/* ----------------------------------------------------
50	 * Common TSP interrupt handling routine
51	 * ----------------------------------------------------
52	 */
53	.macro	handle_tsp_interrupt label
54	/* Enable the SError interrupt */
55	msr	daifclr, #DAIF_ABT_BIT
56
57	save_caller_regs_and_lr
58	bl	tsp_common_int_handler
59	cbz	x0, interrupt_exit_\label
60
61	/*
62	 * This interrupt was not targetted to S-EL1 so send it to
63	 * the monitor and wait for execution to resume.
64	 */
65	smc	#0
66interrupt_exit_\label:
67	restore_caller_regs_and_lr
68	eret
69	.endm
70
71	.globl	tsp_exceptions
72
73	/* -----------------------------------------------------
74	 * TSP exception handlers.
75	 * -----------------------------------------------------
76	 */
77vector_base tsp_exceptions
78	/* -----------------------------------------------------
79	 * Current EL with _sp_el0 : 0x0 - 0x200. No exceptions
80	 * are expected and treated as irrecoverable errors.
81	 * -----------------------------------------------------
82	 */
83vector_entry sync_exception_sp_el0
84	b	plat_panic_handler
85	check_vector_size sync_exception_sp_el0
86
87vector_entry irq_sp_el0
88	b	plat_panic_handler
89	check_vector_size irq_sp_el0
90
91vector_entry fiq_sp_el0
92	b	plat_panic_handler
93	check_vector_size fiq_sp_el0
94
95vector_entry serror_sp_el0
96	b	plat_panic_handler
97	check_vector_size serror_sp_el0
98
99
100	/* -----------------------------------------------------
101	 * Current EL with SPx: 0x200 - 0x400. Only IRQs/FIQs
102	 * are expected and handled
103	 * -----------------------------------------------------
104	 */
105vector_entry sync_exception_sp_elx
106	b	plat_panic_handler
107	check_vector_size sync_exception_sp_elx
108
109vector_entry irq_sp_elx
110	handle_tsp_interrupt irq_sp_elx
111	check_vector_size irq_sp_elx
112
113vector_entry fiq_sp_elx
114	handle_tsp_interrupt fiq_sp_elx
115	check_vector_size fiq_sp_elx
116
117vector_entry serror_sp_elx
118	b	plat_panic_handler
119	check_vector_size serror_sp_elx
120
121
122	/* -----------------------------------------------------
123	 * Lower EL using AArch64 : 0x400 - 0x600. No exceptions
124	 * are handled since TSP does not implement a lower EL
125	 * -----------------------------------------------------
126	 */
127vector_entry sync_exception_aarch64
128	b	plat_panic_handler
129	check_vector_size sync_exception_aarch64
130
131vector_entry irq_aarch64
132	b	plat_panic_handler
133	check_vector_size irq_aarch64
134
135vector_entry fiq_aarch64
136	b	plat_panic_handler
137	check_vector_size fiq_aarch64
138
139vector_entry serror_aarch64
140	b	plat_panic_handler
141	check_vector_size serror_aarch64
142
143
144	/* -----------------------------------------------------
145	 * Lower EL using AArch32 : 0x600 - 0x800. No exceptions
146	 * handled since the TSP does not implement a lower EL.
147	 * -----------------------------------------------------
148	 */
149vector_entry sync_exception_aarch32
150	b	plat_panic_handler
151	check_vector_size sync_exception_aarch32
152
153vector_entry irq_aarch32
154	b	plat_panic_handler
155	check_vector_size irq_aarch32
156
157vector_entry fiq_aarch32
158	b	plat_panic_handler
159	check_vector_size fiq_aarch32
160
161vector_entry serror_aarch32
162	b	plat_panic_handler
163	check_vector_size serror_aarch32
164