1/*-----------------------------------------------------------------------------
2-------------------------------------------------------------------------------
3
4
5 Intel Silvermont Processor Power Management BIOS Reference Code
6
7 Copyright (c) 2006 - 2014, Intel Corporation
8
9  This program and the accompanying materials are licensed and made available under
10  the terms and conditions of the BSD License that accompanies this distribution.
11  The full text of the license may be found at
12  http://opensource.org/licenses/bsd-license.php.
13
14  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16
17
18 Filename:      CPU1CST.ASL
19
20 Revision:      Refer to Readme
21
22 Date:          Refer to Readme
23
24--------------------------------------------------------------------------------
25-------------------------------------------------------------------------------
26
27 This Processor Power Management BIOS Source Code is furnished under license
28 and may only be used or copied in accordance with the terms of the license.
29 The information in this document is furnished for informational use only, is
30 subject to change without notice, and should not be construed as a commitment
31 by Intel Corporation. Intel Corporation assumes no responsibility or liability
32 for any errors or inaccuracies that may appear in this document or any
33 software that may be provided in association with this document.
34
35 Except as permitted by such license, no part of this document may be
36 reproduced, stored in a retrieval system, or transmitted in any form or by
37 any means without the express written consent of Intel Corporation.
38
39 WARNING: You are authorized and licensed to install and use this BIOS code
40 ONLY on an IST PC. This utility may damage any system that does not
41 meet these requirements.
42
43        An IST PC is a computer which
44        (1) Is capable of seamlessly and automatically transitioning among
45        multiple performance states (potentially operating at different
46        efficiency ratings) based upon power source changes, END user
47        preference, processor performance demand, and thermal conditions; and
48        (2) Includes an Intel Pentium II processors, Intel Pentium III
49        processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
50        Processor-M, Intel Pentium M Processor, or any other future Intel
51        processors that incorporates the capability to transition between
52        different performance states by altering some, or any combination of,
53        the following processor attributes: core voltage, core frequency, bus
54        frequency, number of processor cores available, or any other attribute
55        that changes the efficiency (instructions/unit time-power) at which the
56        processor operates.
57
58-------------------------------------------------------------------------------
59-------------------------------------------------------------------------------
60
61NOTES:
62        (1) <TODO> - IF the trap range and port definitions do not match those
63        specified by this reference code, this file must be modified IAW the
64        individual implmentation.
65
66--------------------------------------------------------------------------------
67------------------------------------------------------------------------------*/
68
69
70DefinitionBlock (
71        "APCST.aml",
72        "SSDT",
73        1,
74        "PmRef",
75        "ApCst",
76        0x3000
77        )
78{
79External(\_PR.CPU1, DeviceObj)
80External(\_PR.CPU2, DeviceObj)
81External(\_PR.CPU3, DeviceObj)
82External(\_PR.CPU0._CST)
83
84        Scope(\_PR.CPU1)
85        {
86                Method(_CST,0)
87                {
88                        //
89                        // Return P0's _CST object.
90                        //
91                        Return(\_PR.CPU0._CST)
92                }
93        }
94
95        Scope(\_PR.CPU2)
96        {
97                Method(_CST,0)
98                {
99                        //
100                        // Return P0's _CST object.
101                        //
102                        Return(\_PR.CPU0._CST)
103                }
104        }
105
106        Scope(\_PR.CPU3)
107        {
108                Method(_CST,0)
109                {
110                        //
111                        // Return P0's _CST object.
112                        //
113                        Return(\_PR.CPU0._CST)
114                }
115        }
116}  // End of Definition Block
117