1 /*
2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_helpers.h>
8 #include <assert.h>
9 #include <bakery_lock.h>
10 #include <cpu_data.h>
11 #include <platform.h>
12 #include <string.h>
13
14 /*
15 * Functions in this file implement Bakery Algorithm for mutual exclusion with the
16 * bakery lock data structures in cacheable and Normal memory.
17 *
18 * ARM architecture offers a family of exclusive access instructions to
19 * efficiently implement mutual exclusion with hardware support. However, as
20 * well as depending on external hardware, these instructions have defined
21 * behavior only on certain memory types (cacheable and Normal memory in
22 * particular; see ARMv8 Architecture Reference Manual section B2.10). Use cases
23 * in trusted firmware are such that mutual exclusion implementation cannot
24 * expect that accesses to the lock have the specific type required by the
25 * architecture for these primitives to function (for example, not all
26 * contenders may have address translation enabled).
27 *
28 * This implementation does not use mutual exclusion primitives. It expects
29 * memory regions where the locks reside to be cacheable and Normal.
30 *
31 * Note that the ARM architecture guarantees single-copy atomicity for aligned
32 * accesses regardless of status of address translation.
33 */
34
35 #ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
36 /*
37 * Verify that the platform defined value for the per-cpu space for bakery locks is
38 * a multiple of the cache line size, to prevent multiple CPUs writing to the same
39 * bakery lock cache line
40 *
41 * Using this value, if provided, rather than the linker generated value results in
42 * more efficient code
43 */
44 CASSERT((PLAT_PERCPU_BAKERY_LOCK_SIZE & (CACHE_WRITEBACK_GRANULE - 1)) == 0, \
45 PLAT_PERCPU_BAKERY_LOCK_SIZE_not_cacheline_multiple);
46 #define PERCPU_BAKERY_LOCK_SIZE (PLAT_PERCPU_BAKERY_LOCK_SIZE)
47 #else
48 /*
49 * Use the linker defined symbol which has evaluated the size reqiurement.
50 * This is not as efficient as using a platform defined constant
51 */
52 extern void *__PERCPU_BAKERY_LOCK_SIZE__;
53 #define PERCPU_BAKERY_LOCK_SIZE ((uintptr_t)&__PERCPU_BAKERY_LOCK_SIZE__)
54 #endif
55
56 #define get_bakery_info(cpu_ix, lock) \
57 (bakery_info_t *)((uintptr_t)lock + cpu_ix * PERCPU_BAKERY_LOCK_SIZE)
58
59 #define write_cache_op(addr, cached) \
60 do { \
61 (cached ? dccvac((uintptr_t)addr) :\
62 dcivac((uintptr_t)addr));\
63 dsbish();\
64 } while (0)
65
66 #define read_cache_op(addr, cached) if (cached) \
67 dccivac((uintptr_t)addr)
68
69 /* Helper function to check if the lock is acquired */
is_lock_acquired(const bakery_info_t * my_bakery_info,int is_cached)70 static inline int is_lock_acquired(const bakery_info_t *my_bakery_info,
71 int is_cached)
72 {
73 /*
74 * Even though lock data is updated only by the owning cpu and
75 * appropriate cache maintenance operations are performed,
76 * if the previous update was done when the cpu was not participating
77 * in coherency, then there is a chance that cache maintenance
78 * operations were not propagated to all the caches in the system.
79 * Hence do a `read_cache_op()` prior to read.
80 */
81 read_cache_op(my_bakery_info, is_cached);
82 return !!(bakery_ticket_number(my_bakery_info->lock_data));
83 }
84
bakery_get_ticket(bakery_lock_t * lock,unsigned int me,int is_cached)85 static unsigned int bakery_get_ticket(bakery_lock_t *lock,
86 unsigned int me, int is_cached)
87 {
88 unsigned int my_ticket, their_ticket;
89 unsigned int they;
90 bakery_info_t *my_bakery_info, *their_bakery_info;
91
92 /*
93 * Obtain a reference to the bakery information for this cpu and ensure
94 * it is not NULL.
95 */
96 my_bakery_info = get_bakery_info(me, lock);
97 assert(my_bakery_info);
98
99 /* Prevent recursive acquisition.*/
100 assert(!is_lock_acquired(my_bakery_info, is_cached));
101
102 /*
103 * Tell other contenders that we are through the bakery doorway i.e.
104 * going to allocate a ticket for this cpu.
105 */
106 my_ticket = 0;
107 my_bakery_info->lock_data = make_bakery_data(CHOOSING_TICKET, my_ticket);
108
109 write_cache_op(my_bakery_info, is_cached);
110
111 /*
112 * Iterate through the bakery information of each contender to allocate
113 * the highest ticket number for this cpu.
114 */
115 for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) {
116 if (me == they)
117 continue;
118
119 /*
120 * Get a reference to the other contender's bakery info and
121 * ensure that a stale copy is not read.
122 */
123 their_bakery_info = get_bakery_info(they, lock);
124 assert(their_bakery_info);
125
126 read_cache_op(their_bakery_info, is_cached);
127
128 /*
129 * Update this cpu's ticket number if a higher ticket number is
130 * seen
131 */
132 their_ticket = bakery_ticket_number(their_bakery_info->lock_data);
133 if (their_ticket > my_ticket)
134 my_ticket = their_ticket;
135 }
136
137 /*
138 * Compute ticket; then signal to other contenders waiting for us to
139 * finish calculating our ticket value that we're done
140 */
141 ++my_ticket;
142 my_bakery_info->lock_data = make_bakery_data(CHOSEN_TICKET, my_ticket);
143
144 write_cache_op(my_bakery_info, is_cached);
145
146 return my_ticket;
147 }
148
bakery_lock_get(bakery_lock_t * lock)149 void bakery_lock_get(bakery_lock_t *lock)
150 {
151 unsigned int they, me, is_cached;
152 unsigned int my_ticket, my_prio, their_ticket;
153 bakery_info_t *their_bakery_info;
154 unsigned int their_bakery_data;
155
156 me = plat_my_core_pos();
157 #ifdef AARCH32
158 is_cached = read_sctlr() & SCTLR_C_BIT;
159 #else
160 is_cached = read_sctlr_el3() & SCTLR_C_BIT;
161 #endif
162
163 /* Get a ticket */
164 my_ticket = bakery_get_ticket(lock, me, is_cached);
165
166 /*
167 * Now that we got our ticket, compute our priority value, then compare
168 * with that of others, and proceed to acquire the lock
169 */
170 my_prio = PRIORITY(my_ticket, me);
171 for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) {
172 if (me == they)
173 continue;
174
175 /*
176 * Get a reference to the other contender's bakery info and
177 * ensure that a stale copy is not read.
178 */
179 their_bakery_info = get_bakery_info(they, lock);
180 assert(their_bakery_info);
181
182 /* Wait for the contender to get their ticket */
183 do {
184 read_cache_op(their_bakery_info, is_cached);
185 their_bakery_data = their_bakery_info->lock_data;
186 } while (bakery_is_choosing(their_bakery_data));
187
188 /*
189 * If the other party is a contender, they'll have non-zero
190 * (valid) ticket value. If they do, compare priorities
191 */
192 their_ticket = bakery_ticket_number(their_bakery_data);
193 if (their_ticket && (PRIORITY(their_ticket, they) < my_prio)) {
194 /*
195 * They have higher priority (lower value). Wait for
196 * their ticket value to change (either release the lock
197 * to have it dropped to 0; or drop and probably content
198 * again for the same lock to have an even higher value)
199 */
200 do {
201 wfe();
202 read_cache_op(their_bakery_info, is_cached);
203 } while (their_ticket
204 == bakery_ticket_number(their_bakery_info->lock_data));
205 }
206 }
207 /* Lock acquired */
208 }
209
bakery_lock_release(bakery_lock_t * lock)210 void bakery_lock_release(bakery_lock_t *lock)
211 {
212 bakery_info_t *my_bakery_info;
213 #ifdef AARCH32
214 unsigned int is_cached = read_sctlr() & SCTLR_C_BIT;
215 #else
216 unsigned int is_cached = read_sctlr_el3() & SCTLR_C_BIT;
217 #endif
218
219 my_bakery_info = get_bakery_info(plat_my_core_pos(), lock);
220
221 assert(is_lock_acquired(my_bakery_info, is_cached));
222
223 my_bakery_info->lock_data = 0;
224 write_cache_op(my_bakery_info, is_cached);
225 sev();
226 }
227