1 /*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <board_css_def.h>
8 #include <mmio.h>
9 #include <nic_400.h>
10 #include <platform_def.h>
11 #include <soc_css_def.h>
12
soc_css_init_nic400(void)13 void soc_css_init_nic400(void)
14 {
15 /*
16 * NIC-400 Access Control Initialization
17 *
18 * Define access privileges by setting each corresponding bit to:
19 * 0 = Secure access only
20 * 1 = Non-secure access allowed
21 */
22
23 /*
24 * Allow non-secure access to some SOC regions, excluding UART1, which
25 * remains secure.
26 * Note: This is the NIC-400 device on the SOC
27 */
28 mmio_write_32(SOC_CSS_NIC400_BASE +
29 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_EHCI), ~0);
30 mmio_write_32(SOC_CSS_NIC400_BASE +
31 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_TLX_MASTER), ~0);
32 mmio_write_32(SOC_CSS_NIC400_BASE +
33 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_OHCI), ~0);
34 mmio_write_32(SOC_CSS_NIC400_BASE +
35 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_PL354_SMC), ~0);
36 mmio_write_32(SOC_CSS_NIC400_BASE +
37 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_APB4_BRIDGE), ~0);
38 mmio_write_32(SOC_CSS_NIC400_BASE +
39 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE),
40 ~SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1);
41
42 }
43
44
45 #define PCIE_SECURE_REG 0x3000
46 /* Mask uses REG and MEM access bits */
47 #define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1))
48
soc_css_init_pcie(void)49 void soc_css_init_pcie(void)
50 {
51 #if !PLAT_juno
52 /*
53 * Do not initialize PCIe in emulator environment.
54 * Platform ID register not supported on Juno
55 */
56 if (BOARD_CSS_GET_PLAT_TYPE(BOARD_CSS_PLAT_ID_REG_ADDR) ==
57 BOARD_CSS_PLAT_TYPE_EMULATOR)
58 return;
59 #endif /* PLAT_juno */
60
61 /*
62 * PCIE Root Complex Security settings to enable non-secure
63 * access to config registers.
64 */
65 mmio_write_32(SOC_CSS_PCIE_CONTROL_BASE + PCIE_SECURE_REG,
66 PCIE_SEC_ACCESS_MASK);
67 }
68