1 /*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch.h>
8 #include <arch_helpers.h>
9 #include <arm_gic.h>
10 #include <assert.h>
11 #include <bl31.h>
12 #include <bl_common.h>
13 #include <console.h>
14 #include <cortex_a53.h>
15 #include <debug.h>
16 #include <errno.h>
17 #include <generic_delay_timer.h>
18 #include <mmio.h>
19 #include <plat_arm.h>
20 #include <platform.h>
21 #include <stddef.h>
22 #include <string.h>
23 #include "hi3798cv200.h"
24 #include "plat_private.h"
25 #include "platform_def.h"
26
27 /* Memory ranges for code and RO data sections */
28 #define BL31_RO_BASE (unsigned long)(&__RO_START__)
29 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
30
31 /* Memory ranges for coherent memory section */
32 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
33 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
34
35 static entry_point_info_t bl33_image_ep_info;
36
bl31_plat_get_next_image_ep_info(uint32_t type)37 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
38 {
39 return &bl33_image_ep_info;
40 }
41
bl31_early_platform_setup(bl31_params_t * from_bl2,void * plat_params_from_bl2)42 void bl31_early_platform_setup(bl31_params_t *from_bl2,
43 void *plat_params_from_bl2)
44 {
45 console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
46
47 /* Init console for crash report */
48 plat_crash_console_init();
49
50 bl33_image_ep_info = *from_bl2->bl33_ep_info;
51 }
52
bl31_platform_setup(void)53 void bl31_platform_setup(void)
54 {
55 /* Init arch timer */
56 generic_delay_timer_init();
57
58 /* Init GIC distributor and CPU interface */
59 plat_arm_gic_driver_init();
60 plat_arm_gic_init();
61 }
62
bl31_plat_runtime_setup(void)63 void bl31_plat_runtime_setup(void)
64 {
65 /* do nothing */
66 }
67
bl31_plat_arch_setup(void)68 void bl31_plat_arch_setup(void)
69 {
70 plat_configure_mmu_el3(BL31_RO_BASE,
71 (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
72 BL31_RO_BASE,
73 BL31_RO_LIMIT,
74 BL31_COHERENT_RAM_BASE,
75 BL31_COHERENT_RAM_LIMIT);
76
77 INFO("Boot BL33 from 0x%lx for %lu Bytes\n",
78 bl33_image_ep_info.pc, bl33_image_ep_info.args.arg2);
79 }
80