1 /* This linker script generated from xt-genldscripts.tpp for LSP hifi_hikey_lsp */ 2 /* Linker Script for default link */ 3 MEMORY 4 { 5 sram0_seg : org = 0xC0000000, len = 0x408000 6 old_vlpd_seg : org = 0xC0408000, len = 0x10000 7 efr_fr_hr_vlpd_seg : org = 0xC0418000, len = 0x10000 8 amr_vlpd_seg : org = 0xC0428000, len = 0x10000 9 amrwb_vlpd_seg : org = 0xC0438000, len = 0x10000 10 evrc_evrcb_vlpt_seg : org = 0xC0448000, len = 0x48000 11 efr_fr_hr_vlpt_seg : org = 0xC0490000, len = 0x30000 12 amr_vlpt_seg : org = 0xC04C0000, len = 0x20000 13 amrwb_vlpt_seg : org = 0xC04E0000, len = 0x30000 14 vlpt_seg : org = 0xC0510000, len = 0x48000 15 vlpd_seg : org = 0xC0558000, len = 0x20000 16 ulpp_seg : org = 0xC0578000, len = 0x40000 17 dtsv3_seg : org = 0xC05B8000, len = 0x20000 18 dtsv4_seg : org = 0xC05D8000, len = 0x28000 19 dram0_0_seg : org = 0xE8058000, len = 0x28000 20 iram0_0_seg : org = 0xE8080000, len = 0x300 21 iram0_1_seg : org = 0xE8080300, len = 0x100 22 iram0_2_seg : org = 0xE8080400, len = 0x178 23 iram0_3_seg : org = 0xE8080578, len = 0x8 24 iram0_4_seg : org = 0xE8080580, len = 0x38 25 iram0_5_seg : org = 0xE80805B8, len = 0x8 26 iram0_6_seg : org = 0xE80805C0, len = 0x38 27 iram0_7_seg : org = 0xE80805F8, len = 0x8 28 iram0_8_seg : org = 0xE8080600, len = 0x38 29 iram0_9_seg : org = 0xE8080638, len = 0x8 30 iram0_10_seg : org = 0xE8080640, len = 0x38 31 iram0_11_seg : org = 0xE8080678, len = 0x48 32 iram0_12_seg : org = 0xE80806C0, len = 0x38 33 iram0_13_seg : org = 0xE80806F8, len = 0x8 34 iram0_14_seg : org = 0xE8080700, len = 0x38 35 iram0_15_seg : org = 0xE8080738, len = 0x8 36 iram0_16_seg : org = 0xE8080740, len = 0x38 37 iram0_17_seg : org = 0xE8080778, len = 0x48 38 iram0_18_seg : org = 0xE80807C0, len = 0x40 39 iram0_19_seg : org = 0xE8080800, len = 0xB800 40 } 41 42 PHDRS 43 { 44 sram0_phdr PT_LOAD; 45 sram0_bss_phdr PT_LOAD; 46 old_vlpd_phdr PT_LOAD; 47 old_vlpd_bss_phdr PT_LOAD; 48 efr_fr_hr_vlpd_phdr PT_LOAD; 49 efr_fr_hr_vlpd_bss_phdr PT_LOAD; 50 amr_vlpd_phdr PT_LOAD; 51 amr_vlpd_bss_phdr PT_LOAD; 52 amrwb_vlpd_phdr PT_LOAD; 53 amrwb_vlpd_bss_phdr PT_LOAD; 54 evrc_evrcb_vlpt_phdr PT_LOAD; 55 efr_fr_hr_vlpt_phdr PT_LOAD; 56 amr_vlpt_phdr PT_LOAD; 57 amrwb_vlpt_phdr PT_LOAD; 58 vlpt_phdr PT_LOAD; 59 vlpd_phdr PT_LOAD; 60 ulpp_phdr PT_LOAD; 61 ulpp_bss_phdr PT_LOAD; 62 dtsv3_phdr PT_LOAD; 63 dtsv3_bss_phdr PT_LOAD; 64 dtsv4_phdr PT_LOAD; 65 dtsv4_bss_phdr PT_LOAD; 66 dram0_0_phdr PT_LOAD; 67 dram0_0_bss_phdr PT_LOAD; 68 iram0_0_phdr PT_LOAD; 69 iram0_1_phdr PT_LOAD; 70 iram0_2_phdr PT_LOAD; 71 iram0_3_phdr PT_LOAD; 72 iram0_4_phdr PT_LOAD; 73 iram0_5_phdr PT_LOAD; 74 iram0_6_phdr PT_LOAD; 75 iram0_7_phdr PT_LOAD; 76 iram0_8_phdr PT_LOAD; 77 iram0_9_phdr PT_LOAD; 78 iram0_10_phdr PT_LOAD; 79 iram0_11_phdr PT_LOAD; 80 iram0_12_phdr PT_LOAD; 81 iram0_13_phdr PT_LOAD; 82 iram0_14_phdr PT_LOAD; 83 iram0_15_phdr PT_LOAD; 84 iram0_16_phdr PT_LOAD; 85 iram0_17_phdr PT_LOAD; 86 iram0_18_phdr PT_LOAD; 87 iram0_19_phdr PT_LOAD; 88 } 89 90 91 /* Default entry point: */ 92 ENTRY(_ResetVector) 93 94 /* Memory boundary addresses: */ 95 _memmap_mem_iram0_start = 0xe8080000; 96 _memmap_mem_iram0_end = 0xe808c000; 97 _memmap_mem_dram0_start = 0xe8058000; 98 _memmap_mem_dram0_end = 0xe8080000; 99 _memmap_mem_sram_start = 0xc0000000; 100 _memmap_mem_sram_end = 0xc0600000; 101 102 /* Memory segment boundary addresses: */ 103 _memmap_seg_sram0_start = 0xc0000000; 104 _memmap_seg_sram0_max = 0xc0408000; 105 _memmap_seg_old_vlpd_start = 0xc0408000; 106 _memmap_seg_old_vlpd_max = 0xc0418000; 107 _memmap_seg_efr_fr_hr_vlpd_start = 0xc0418000; 108 _memmap_seg_efr_fr_hr_vlpd_max = 0xc0428000; 109 _memmap_seg_amr_vlpd_start = 0xc0428000; 110 _memmap_seg_amr_vlpd_max = 0xc0438000; 111 _memmap_seg_amrwb_vlpd_start = 0xc0438000; 112 _memmap_seg_amrwb_vlpd_max = 0xc0448000; 113 _memmap_seg_evrc_evrcb_vlpt_start = 0xc0448000; 114 _memmap_seg_evrc_evrcb_vlpt_max = 0xc0490000; 115 _memmap_seg_efr_fr_hr_vlpt_start = 0xc0490000; 116 _memmap_seg_efr_fr_hr_vlpt_max = 0xc04c0000; 117 _memmap_seg_amr_vlpt_start = 0xc04c0000; 118 _memmap_seg_amr_vlpt_max = 0xc04e0000; 119 _memmap_seg_amrwb_vlpt_start = 0xc04e0000; 120 _memmap_seg_amrwb_vlpt_max = 0xc0510000; 121 _memmap_seg_vlpt_start = 0xc0510000; 122 _memmap_seg_vlpt_max = 0xc0558000; 123 _memmap_seg_vlpd_start = 0xc0558000; 124 _memmap_seg_vlpd_max = 0xc0578000; 125 _memmap_seg_ulpp_start = 0xc0578000; 126 _memmap_seg_ulpp_max = 0xc05b8000; 127 _memmap_seg_dtsv3_start = 0xc05b8000; 128 _memmap_seg_dtsv3_max = 0xc05d8000; 129 _memmap_seg_dtsv4_start = 0xc05d8000; 130 _memmap_seg_dtsv4_max = 0xc0600000; 131 _memmap_seg_dram0_0_start = 0xe8058000; 132 _memmap_seg_dram0_0_max = 0xe8080000; 133 _memmap_seg_iram0_0_start = 0xe8080000; 134 _memmap_seg_iram0_0_max = 0xe8080300; 135 _memmap_seg_iram0_1_start = 0xe8080300; 136 _memmap_seg_iram0_1_max = 0xe8080400; 137 _memmap_seg_iram0_2_start = 0xe8080400; 138 _memmap_seg_iram0_2_max = 0xe8080578; 139 _memmap_seg_iram0_3_start = 0xe8080578; 140 _memmap_seg_iram0_3_max = 0xe8080580; 141 _memmap_seg_iram0_4_start = 0xe8080580; 142 _memmap_seg_iram0_4_max = 0xe80805b8; 143 _memmap_seg_iram0_5_start = 0xe80805b8; 144 _memmap_seg_iram0_5_max = 0xe80805c0; 145 _memmap_seg_iram0_6_start = 0xe80805c0; 146 _memmap_seg_iram0_6_max = 0xe80805f8; 147 _memmap_seg_iram0_7_start = 0xe80805f8; 148 _memmap_seg_iram0_7_max = 0xe8080600; 149 _memmap_seg_iram0_8_start = 0xe8080600; 150 _memmap_seg_iram0_8_max = 0xe8080638; 151 _memmap_seg_iram0_9_start = 0xe8080638; 152 _memmap_seg_iram0_9_max = 0xe8080640; 153 _memmap_seg_iram0_10_start = 0xe8080640; 154 _memmap_seg_iram0_10_max = 0xe8080678; 155 _memmap_seg_iram0_11_start = 0xe8080678; 156 _memmap_seg_iram0_11_max = 0xe80806c0; 157 _memmap_seg_iram0_12_start = 0xe80806c0; 158 _memmap_seg_iram0_12_max = 0xe80806f8; 159 _memmap_seg_iram0_13_start = 0xe80806f8; 160 _memmap_seg_iram0_13_max = 0xe8080700; 161 _memmap_seg_iram0_14_start = 0xe8080700; 162 _memmap_seg_iram0_14_max = 0xe8080738; 163 _memmap_seg_iram0_15_start = 0xe8080738; 164 _memmap_seg_iram0_15_max = 0xe8080740; 165 _memmap_seg_iram0_16_start = 0xe8080740; 166 _memmap_seg_iram0_16_max = 0xe8080778; 167 _memmap_seg_iram0_17_start = 0xe8080778; 168 _memmap_seg_iram0_17_max = 0xe80807c0; 169 _memmap_seg_iram0_18_start = 0xe80807c0; 170 _memmap_seg_iram0_18_max = 0xe8080800; 171 _memmap_seg_iram0_19_start = 0xe8080800; 172 _memmap_seg_iram0_19_max = 0xe808c000; 173 174 _rom_store_table = 0; 175 PROVIDE(_memmap_vecbase_reset = 0xe8080400); 176 PROVIDE(_memmap_reset_vector = 0xe8080000); 177 /* Various memory-map dependent cache attribute settings: */ 178 _memmap_cacheattr_wb_base = 0x44000000; 179 _memmap_cacheattr_wt_base = 0x11000000; 180 _memmap_cacheattr_bp_base = 0x22000000; 181 _memmap_cacheattr_unused_mask = 0x00FFFFFF; 182 _memmap_cacheattr_wb_trapnull = 0x4422222F; 183 _memmap_cacheattr_wba_trapnull = 0x4422222F; 184 _memmap_cacheattr_wbna_trapnull = 0x5522222F; 185 _memmap_cacheattr_wt_trapnull = 0x1122222F; 186 _memmap_cacheattr_bp_trapnull = 0x2222222F; 187 _memmap_cacheattr_wb_strict = 0x44FFFFFF; 188 _memmap_cacheattr_wt_strict = 0x11FFFFFF; 189 _memmap_cacheattr_bp_strict = 0x22FFFFFF; 190 _memmap_cacheattr_wb_allvalid = 0x44222222; 191 _memmap_cacheattr_wt_allvalid = 0x11222222; 192 _memmap_cacheattr_bp_allvalid = 0x22222222; 193 PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); 194 195 SECTIONS 196 { 197 198 .vlpd.rodata : ALIGN(4) 199 { 200 _vlpd_rodata_start = ABSOLUTE(.); 201 *(.vlpd.rodata) 202 _vlpd_rodata_end = ABSOLUTE(.); 203 } >old_vlpd_seg :old_vlpd_phdr 204 205 .vlpd.data : ALIGN(4) 206 { 207 _vlpd_data_start = ABSOLUTE(.); 208 *(.vlpd.data) 209 _vlpd_data_end = ABSOLUTE(.); 210 } >old_vlpd_seg :old_vlpd_phdr 211 bss(NOLOAD)212 .vlpd.bss (NOLOAD) : ALIGN(8) 213 { 214 . = ALIGN (8); 215 _vlpd_bss_start = ABSOLUTE(.); 216 *(.vlpd.bss) 217 . = ALIGN (8); 218 _vlpd_bss_end = ABSOLUTE(.); 219 _memmap_seg_old_vlpd_end = ALIGN(0x8); 220 } >old_vlpd_seg :old_vlpd_bss_phdr 221 222 .efr_fr_hr_vlpd.rodata : ALIGN(4) 223 { 224 _efr_fr_hr_vlpd_rodata_start = ABSOLUTE(.); 225 *(.efr_fr_hr_vlpd.rodata) 226 _efr_fr_hr_vlpd_rodata_end = ABSOLUTE(.); 227 } >efr_fr_hr_vlpd_seg :efr_fr_hr_vlpd_phdr 228 229 .efr_fr_hr_vlpd.data : ALIGN(4) 230 { 231 _efr_fr_hr_vlpd_data_start = ABSOLUTE(.); 232 *(.efr_fr_hr_vlpd.data) 233 _efr_fr_hr_vlpd_data_end = ABSOLUTE(.); 234 } >efr_fr_hr_vlpd_seg :efr_fr_hr_vlpd_phdr 235 bss(NOLOAD)236 .efr_fr_hr_vlpd.bss (NOLOAD) : ALIGN(8) 237 { 238 . = ALIGN (8); 239 _efr_fr_hr_vlpd_bss_start = ABSOLUTE(.); 240 *(.efr_fr_hr_vlpd.bss) 241 . = ALIGN (8); 242 _efr_fr_hr_vlpd_bss_end = ABSOLUTE(.); 243 _memmap_seg_efr_fr_hr_vlpd_end = ALIGN(0x8); 244 } >efr_fr_hr_vlpd_seg :efr_fr_hr_vlpd_bss_phdr 245 246 .amr_vlpd.rodata : ALIGN(4) 247 { 248 _amr_vlpd_rodata_start = ABSOLUTE(.); 249 *(.amr_vlpd.rodata) 250 _amr_vlpd_rodata_end = ABSOLUTE(.); 251 } >amr_vlpd_seg :amr_vlpd_phdr 252 253 .amr_vlpd.data : ALIGN(4) 254 { 255 _amr_vlpd_data_start = ABSOLUTE(.); 256 *(.amr_vlpd.data) 257 _amr_vlpd_data_end = ABSOLUTE(.); 258 } >amr_vlpd_seg :amr_vlpd_phdr 259 bss(NOLOAD)260 .amr_vlpd.bss (NOLOAD) : ALIGN(8) 261 { 262 . = ALIGN (8); 263 _amr_vlpd_bss_start = ABSOLUTE(.); 264 *(.amr_vlpd.bss) 265 . = ALIGN (8); 266 _amr_vlpd_bss_end = ABSOLUTE(.); 267 _memmap_seg_amr_vlpd_end = ALIGN(0x8); 268 } >amr_vlpd_seg :amr_vlpd_bss_phdr 269 270 .amrwb_vlpd.rodata : ALIGN(4) 271 { 272 _amrwb_vlpd_rodata_start = ABSOLUTE(.); 273 *(.amrwb_vlpd.rodata) 274 _amrwb_vlpd_rodata_end = ABSOLUTE(.); 275 } >amrwb_vlpd_seg :amrwb_vlpd_phdr 276 277 .amrwb_vlpd.data : ALIGN(4) 278 { 279 _amrwb_vlpd_data_start = ABSOLUTE(.); 280 *(.amrwb_vlpd.data) 281 _amrwb_vlpd_data_end = ABSOLUTE(.); 282 } >amrwb_vlpd_seg :amrwb_vlpd_phdr 283 bss(NOLOAD)284 .amrwb_vlpd.bss (NOLOAD) : ALIGN(8) 285 { 286 . = ALIGN (8); 287 _amrwb_vlpd_bss_start = ABSOLUTE(.); 288 *(.amrwb_vlpd.bss) 289 . = ALIGN (8); 290 _amrwb_vlpd_bss_end = ABSOLUTE(.); 291 _memmap_seg_amrwb_vlpd_end = ALIGN(0x8); 292 } >amrwb_vlpd_seg :amrwb_vlpd_bss_phdr 293 294 .evrc_evrcb_vlpt.text : ALIGN(4) 295 { 296 _evrc_evrcb_vlpt_text_start = ABSOLUTE(.); 297 *(.evrc_evrcb_vlpt.literal .evrc_evrcb_vlpt.text) 298 _evrc_evrcb_vlpt_text_end = ABSOLUTE(.); 299 _memmap_seg_evrc_evrcb_vlpt_end = ALIGN(0x8); 300 } >evrc_evrcb_vlpt_seg :evrc_evrcb_vlpt_phdr 301 302 .efr_fr_hr_vlpt.text : ALIGN(4) 303 { 304 _efr_fr_hr_vlpt_text_start = ABSOLUTE(.); 305 *(.efr_fr_hr_vlpt.literal .efr_fr_hr_vlpt.text) 306 _efr_fr_hr_vlpt_text_end = ABSOLUTE(.); 307 _memmap_seg_efr_fr_hr_vlpt_end = ALIGN(0x8); 308 } >efr_fr_hr_vlpt_seg :efr_fr_hr_vlpt_phdr 309 310 .amr_vlpt.text : ALIGN(4) 311 { 312 _amr_vlpt_text_start = ABSOLUTE(.); 313 *(.amr_vlpt.literal .amr_vlpt.text) 314 _amr_vlpt_text_end = ABSOLUTE(.); 315 _memmap_seg_amr_vlpt_end = ALIGN(0x8); 316 } >amr_vlpt_seg :amr_vlpt_phdr 317 318 .amrwb_vlpt.text : ALIGN(4) 319 { 320 _amrwb_vlpt_text_start = ABSOLUTE(.); 321 *(.amrwb_vlpt.literal .amrwb_vlpt.text) 322 _amrwb_vlpt_text_end = ABSOLUTE(.); 323 _memmap_seg_amrwb_vlpt_end = ALIGN(0x8); 324 } >amrwb_vlpt_seg :amrwb_vlpt_phdr 325 326 .vlpt.text : ALIGN(4) 327 { 328 _vlpt_text_start = ABSOLUTE(.); 329 *(.vlpt.literal .vlpt.text) 330 _vlpt_text_end = ABSOLUTE(.); 331 _memmap_seg_vlpt_end = ALIGN(0x8); 332 } >vlpt_seg :vlpt_phdr 333 334 .low_power_dyn_alloc : ALIGN(4) 335 { 336 _low_power_dyn_alloc_start = ABSOLUTE(.); 337 *(.low_power_dyn_alloc) 338 _low_power_dyn_alloc_end = ABSOLUTE(.); 339 _memmap_seg_vlpd_end = ALIGN(0x8); 340 } >vlpd_seg :vlpd_phdr 341 342 .ulpp.rodata : ALIGN(4) 343 { 344 _ulpp_rodata_start = ABSOLUTE(.); 345 *(.ulpp.rodata) 346 _ulpp_rodata_end = ABSOLUTE(.); 347 } >ulpp_seg :ulpp_phdr 348 349 .ulpp.data : ALIGN(4) 350 { 351 _ulpp_data_start = ABSOLUTE(.); 352 *(.ulpp.data) 353 _ulpp_data_end = ABSOLUTE(.); 354 } >ulpp_seg :ulpp_phdr 355 356 .ulpp.text : ALIGN(4) 357 { 358 _ulpp_text_start = ABSOLUTE(.); 359 *(.ulpp.literal .ulpp.text) 360 _ulpp_text_end = ABSOLUTE(.); 361 } >ulpp_seg :ulpp_phdr 362 bss(NOLOAD)363 .ulpp.bss (NOLOAD) : ALIGN(8) 364 { 365 . = ALIGN (8); 366 _ulpp_bss_start = ABSOLUTE(.); 367 *(.ulpp.bss) 368 . = ALIGN (8); 369 _ulpp_bss_end = ABSOLUTE(.); 370 _memmap_seg_ulpp_end = ALIGN(0x8); 371 } >ulpp_seg :ulpp_bss_phdr 372 373 .dtsv3.rodata : ALIGN(4) 374 { 375 _dtsv3_rodata_start = ABSOLUTE(.); 376 *(.dtsv3.rodata) 377 _dtsv3_rodata_end = ABSOLUTE(.); 378 } >dtsv3_seg :dtsv3_phdr 379 380 .dtsv3.data : ALIGN(4) 381 { 382 _dtsv3_data_start = ABSOLUTE(.); 383 *(.dtsv3.data) 384 _dtsv3_data_end = ABSOLUTE(.); 385 } >dtsv3_seg :dtsv3_phdr 386 387 .dtsv3.text : ALIGN(4) 388 { 389 _dtsv3_text_start = ABSOLUTE(.); 390 *(.dtsv3.literal .dtsv3.text) 391 _dtsv3_text_end = ABSOLUTE(.); 392 } >dtsv3_seg :dtsv3_phdr 393 bss(NOLOAD)394 .dtsv3.bss (NOLOAD) : ALIGN(8) 395 { 396 . = ALIGN (8); 397 _dtsv3_bss_start = ABSOLUTE(.); 398 *(.dtsv3.bss) 399 . = ALIGN (8); 400 _dtsv3_bss_end = ABSOLUTE(.); 401 _memmap_seg_dtsv3_end = ALIGN(0x8); 402 } >dtsv3_seg :dtsv3_bss_phdr 403 404 .dtsv4.rodata : ALIGN(4) 405 { 406 _dtsv4_rodata_start = ABSOLUTE(.); 407 *(.dtsv4.rodata) 408 _dtsv4_rodata_end = ABSOLUTE(.); 409 } >dtsv4_seg :dtsv4_phdr 410 411 .dtsv4.data : ALIGN(4) 412 { 413 _dtsv4_data_start = ABSOLUTE(.); 414 *(.dtsv4.data) 415 _dtsv4_data_end = ABSOLUTE(.); 416 } >dtsv4_seg :dtsv4_phdr 417 418 .dtsv4.text : ALIGN(4) 419 { 420 _dtsv4_text_start = ABSOLUTE(.); 421 *(.dtsv4.literal .dtsv4.text) 422 _dtsv4_text_end = ABSOLUTE(.); 423 } >dtsv4_seg :dtsv4_phdr 424 bss(NOLOAD)425 .dtsv4.bss (NOLOAD) : ALIGN(8) 426 { 427 . = ALIGN (8); 428 _dtsv4_bss_start = ABSOLUTE(.); 429 *(.dtsv4.bss) 430 . = ALIGN (8); 431 _dtsv4_bss_end = ABSOLUTE(.); 432 _memmap_seg_dtsv4_end = ALIGN(0x8); 433 } >dtsv4_seg :dtsv4_bss_phdr 434 435 .dram0.rodata : ALIGN(4) 436 { 437 _dram0_rodata_start = ABSOLUTE(.); 438 *(.dram0.rodata) 439 *(.dram.rodata) 440 _dram0_rodata_end = ABSOLUTE(.); 441 } >dram0_0_seg :dram0_0_phdr 442 443 .dram0.literal : ALIGN(4) 444 { 445 _dram0_literal_start = ABSOLUTE(.); 446 *(.dram0.literal) 447 *(.dram.literal) 448 _dram0_literal_end = ABSOLUTE(.); 449 } >dram0_0_seg :dram0_0_phdr 450 451 .dram0.data : ALIGN(4) 452 { 453 _dram0_data_start = ABSOLUTE(.); 454 *(.dram0.data) 455 *(.dram.data) 456 _dram0_data_end = ABSOLUTE(.); 457 } >dram0_0_seg :dram0_0_phdr 458 bss(NOLOAD)459 .dram0.bss (NOLOAD) : ALIGN(8) 460 { 461 . = ALIGN (8); 462 _dram0_bss_start = ABSOLUTE(.); 463 *(.dram0.bss) 464 *(.om.debug.bss) 465 *(.os.stack.bss) 466 . = ALIGN (8); 467 _dram0_bss_end = ABSOLUTE(.); 468 _end = ALIGN(0x8); 469 PROVIDE(end = ALIGN(0x8)); 470 _stack_sentry = ALIGN(0x8); 471 _memmap_seg_dram0_0_end = ALIGN(0x8); 472 } >dram0_0_seg :dram0_0_bss_phdr 473 __stack = 0xe8080000; 474 _heap_sentry = 0xe8080000; 475 476 .ResetVector.text : ALIGN(4) 477 { 478 _ResetVector_text_start = ABSOLUTE(.); 479 KEEP (*(.ResetVector.text)) 480 _ResetVector_text_end = ABSOLUTE(.); 481 _memmap_seg_iram0_0_end = ALIGN(0x8); 482 } >iram0_0_seg :iram0_0_phdr 483 484 .Reset.literal : ALIGN(4) 485 { 486 _Reset_literal_start = ABSOLUTE(.); 487 *(.Reset.literal) 488 _Reset_literal_end = ABSOLUTE(.); 489 _memmap_seg_iram0_1_end = ALIGN(0x8); 490 } >iram0_1_seg :iram0_1_phdr 491 492 .WindowVectors.text : ALIGN(4) 493 { 494 _WindowVectors_text_start = ABSOLUTE(.); 495 KEEP (*(.WindowVectors.text)) 496 _WindowVectors_text_end = ABSOLUTE(.); 497 _memmap_seg_iram0_2_end = ALIGN(0x8); 498 } >iram0_2_seg :iram0_2_phdr 499 500 .Level2InterruptVector.literal : ALIGN(4) 501 { 502 _Level2InterruptVector_literal_start = ABSOLUTE(.); 503 *(.Level2InterruptVector.literal) 504 _Level2InterruptVector_literal_end = ABSOLUTE(.); 505 _memmap_seg_iram0_3_end = ALIGN(0x8); 506 } >iram0_3_seg :iram0_3_phdr 507 508 .Level2InterruptVector.text : ALIGN(4) 509 { 510 _Level2InterruptVector_text_start = ABSOLUTE(.); 511 KEEP (*(.Level2InterruptVector.text)) 512 _Level2InterruptVector_text_end = ABSOLUTE(.); 513 _memmap_seg_iram0_4_end = ALIGN(0x8); 514 } >iram0_4_seg :iram0_4_phdr 515 516 .Level3InterruptVector.literal : ALIGN(4) 517 { 518 _Level3InterruptVector_literal_start = ABSOLUTE(.); 519 *(.Level3InterruptVector.literal) 520 _Level3InterruptVector_literal_end = ABSOLUTE(.); 521 _memmap_seg_iram0_5_end = ALIGN(0x8); 522 } >iram0_5_seg :iram0_5_phdr 523 524 .Level3InterruptVector.text : ALIGN(4) 525 { 526 _Level3InterruptVector_text_start = ABSOLUTE(.); 527 KEEP (*(.Level3InterruptVector.text)) 528 _Level3InterruptVector_text_end = ABSOLUTE(.); 529 _memmap_seg_iram0_6_end = ALIGN(0x8); 530 } >iram0_6_seg :iram0_6_phdr 531 532 .Level4InterruptVector.literal : ALIGN(4) 533 { 534 _Level4InterruptVector_literal_start = ABSOLUTE(.); 535 *(.Level4InterruptVector.literal) 536 _Level4InterruptVector_literal_end = ABSOLUTE(.); 537 _memmap_seg_iram0_7_end = ALIGN(0x8); 538 } >iram0_7_seg :iram0_7_phdr 539 540 .Level4InterruptVector.text : ALIGN(4) 541 { 542 _Level4InterruptVector_text_start = ABSOLUTE(.); 543 KEEP (*(.Level4InterruptVector.text)) 544 _Level4InterruptVector_text_end = ABSOLUTE(.); 545 _memmap_seg_iram0_8_end = ALIGN(0x8); 546 } >iram0_8_seg :iram0_8_phdr 547 548 .DebugExceptionVector.literal : ALIGN(4) 549 { 550 _DebugExceptionVector_literal_start = ABSOLUTE(.); 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583 *(.KernelExceptionVector.literal) 584 _KernelExceptionVector_literal_end = ABSOLUTE(.); 585 _memmap_seg_iram0_13_end = ALIGN(0x8); 586 } >iram0_13_seg :iram0_13_phdr 587 588 .KernelExceptionVector.text : ALIGN(4) 589 { 590 _KernelExceptionVector_text_start = ABSOLUTE(.); 591 KEEP (*(.KernelExceptionVector.text)) 592 _KernelExceptionVector_text_end = ABSOLUTE(.); 593 _memmap_seg_iram0_14_end = ALIGN(0x8); 594 } >iram0_14_seg :iram0_14_phdr 595 596 .UserExceptionVector.literal : ALIGN(4) 597 { 598 _UserExceptionVector_literal_start = ABSOLUTE(.); 599 *(.UserExceptionVector.literal) 600 _UserExceptionVector_literal_end = ABSOLUTE(.); 601 _memmap_seg_iram0_15_end = ALIGN(0x8); 602 } >iram0_15_seg :iram0_15_phdr 603 604 .UserExceptionVector.text : ALIGN(4) 605 { 606 _UserExceptionVector_text_start = ABSOLUTE(.); 607 KEEP (*(.UserExceptionVector.text)) 608 _UserExceptionVector_text_end = ABSOLUTE(.); 609 _memmap_seg_iram0_16_end = ALIGN(0x8); 610 } >iram0_16_seg :iram0_16_phdr 611 612 .DoubleExceptionVector.literal : ALIGN(4) 613 { 614 _DoubleExceptionVector_literal_start = ABSOLUTE(.); 615 *(.DoubleExceptionVector.literal) 616 _DoubleExceptionVector_literal_end = ABSOLUTE(.); 617 _memmap_seg_iram0_17_end = ALIGN(0x8); 618 } >iram0_17_seg :iram0_17_phdr 619 620 .DoubleExceptionVector.text : ALIGN(4) 621 { 622 _DoubleExceptionVector_text_start = ABSOLUTE(.); 623 KEEP (*(.DoubleExceptionVector.text)) 624 _DoubleExceptionVector_text_end = ABSOLUTE(.); 625 _memmap_seg_iram0_18_end = ALIGN(0x8); 626 } >iram0_18_seg :iram0_18_phdr 627 628 .Reset.text : ALIGN(4) 629 { 630 _Reset_text_start = ABSOLUTE(.); 631 *(.Reset.text) 632 _Reset_text_end = ABSOLUTE(.); 633 } >iram0_19_seg :iram0_19_phdr 634 635 .iram0.text : ALIGN(4) 636 { 637 _iram0_text_start = ABSOLUTE(.); 638 *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) 639 _iram0_text_end = ABSOLUTE(.); 640 _memmap_seg_iram0_19_end = ALIGN(0x8); 641 } >iram0_19_seg :iram0_19_phdr 642 643 .sram.shareaddr : ALIGN(4) 644 { 645 _sram_shareaddr_start = ABSOLUTE(.); 646 *(.sram.shareaddr) 647 _sram_shareaddr_end = ABSOLUTE(.); 648 } >sram0_seg :sram0_phdr 649 650 .sram.rodata : ALIGN(4) 651 { 652 _sram_rodata_start = ABSOLUTE(.); 653 *(.sram.rodata) 654 _sram_rodata_end = ABSOLUTE(.); 655 } >sram0_seg :sram0_phdr 656 657 .rodata : ALIGN(4) 658 { 659 _rodata_start = ABSOLUTE(.); 660 *(.rodata) 661 *(.rodata.*) 662 *(.gnu.linkonce.r.*) 663 *(.rodata1) 664 __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); 665 KEEP (*(.xt_except_table)) 666 KEEP (*(.gcc_except_table)) 667 *(.gnu.linkonce.e.*) 668 *(.gnu.version_r) 669 KEEP (*(.eh_frame)) 670 /* C++ constructor and destructor tables, properly ordered: */ 671 KEEP (*crtbegin.o(.ctors)) 672 KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) 673 KEEP (*(SORT(.ctors.*))) 674 KEEP (*(.ctors)) 675 KEEP (*crtbegin.o(.dtors)) 676 KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) 677 KEEP (*(SORT(.dtors.*))) 678 KEEP (*(.dtors)) 679 /* C++ exception handlers table: */ 680 __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); 681 *(.xt_except_desc) 682 *(.gnu.linkonce.h.*) 683 __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); 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