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Searched refs:InAt (Results 1 – 16 of 16) sorted by relevance

/art/compiler/optimizing/
Dcode_generator_vector_x86.cc78 __ movd(dst, locations->InAt(0).AsRegister<Register>()); in VisitVecReplicateScalar()
86 __ movd(dst, locations->InAt(0).AsRegister<Register>()); in VisitVecReplicateScalar()
92 __ movd(dst, locations->InAt(0).AsRegister<Register>()); in VisitVecReplicateScalar()
98 __ movd(dst, locations->InAt(0).AsRegisterPairLow<Register>()); in VisitVecReplicateScalar()
99 __ movd(tmp, locations->InAt(0).AsRegisterPairHigh<Register>()); in VisitVecReplicateScalar()
106 DCHECK(locations->InAt(0).Equals(locations->Out())); in VisitVecReplicateScalar()
111 DCHECK(locations->InAt(0).Equals(locations->Out())); in VisitVecReplicateScalar()
149 XmmRegister src = locations->InAt(0).AsFpuRegister<XmmRegister>(); in VisitVecExtractScalar()
175 DCHECK(locations->InAt(0).Equals(locations->Out())); // no code required in VisitVecExtractScalar()
217 XmmRegister src = locations->InAt(0).AsFpuRegister<XmmRegister>(); in VisitVecReduce()
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Dcode_generator_vector_x86_64.cc73 __ movd(dst, locations->InAt(0).AsRegister<CpuRegister>(), /*64-bit*/ false); in VisitVecReplicateScalar()
81 __ movd(dst, locations->InAt(0).AsRegister<CpuRegister>(), /*64-bit*/ false); in VisitVecReplicateScalar()
87 __ movd(dst, locations->InAt(0).AsRegister<CpuRegister>(), /*64-bit*/ false); in VisitVecReplicateScalar()
92 __ movd(dst, locations->InAt(0).AsRegister<CpuRegister>(), /*64-bit*/ true); in VisitVecReplicateScalar()
97 DCHECK(locations->InAt(0).Equals(locations->Out())); in VisitVecReplicateScalar()
102 DCHECK(locations->InAt(0).Equals(locations->Out())); in VisitVecReplicateScalar()
137 XmmRegister src = locations->InAt(0).AsFpuRegister<XmmRegister>(); in VisitVecExtractScalar()
158 DCHECK(locations->InAt(0).Equals(locations->Out())); // no code required in VisitVecExtractScalar()
200 XmmRegister src = locations->InAt(0).AsFpuRegister<XmmRegister>(); in VisitVecReduce()
246 XmmRegister src = locations->InAt(0).AsFpuRegister<XmmRegister>(); in VisitVecCnv()
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Dcode_generator_vector_arm_vixl.cc94 vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); in VisitVecExtractScalar()
136 vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); in VisitVecReduce()
173 vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); in VisitVecNeg()
202 vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); in VisitVecAbs()
229 vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); in VisitVecNot()
276 vixl32::DRegister lhs = DRegisterFrom(locations->InAt(0)); in VisitVecAdd()
277 vixl32::DRegister rhs = DRegisterFrom(locations->InAt(1)); in VisitVecAdd()
306 vixl32::DRegister lhs = DRegisterFrom(locations->InAt(0)); in VisitVecSaturationAdd()
307 vixl32::DRegister rhs = DRegisterFrom(locations->InAt(1)); in VisitVecSaturationAdd()
338 vixl32::DRegister lhs = DRegisterFrom(locations->InAt(0)); in VisitVecHalvingAdd()
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Dcode_generator_vector_arm64.cc83 Location src_loc = locations->InAt(0); in VisitVecReplicateScalar()
169 VRegister src = VRegisterFrom(locations->InAt(0)); in VisitVecExtractScalar()
183 DCHECK(locations->InAt(0).Equals(locations->Out())); // no code required in VisitVecExtractScalar()
224 VRegister src = VRegisterFrom(locations->InAt(0)); in VisitVecReduce()
264 VRegister src = VRegisterFrom(locations->InAt(0)); in VisitVecCnv()
282 VRegister src = VRegisterFrom(locations->InAt(0)); in VisitVecNeg()
323 VRegister src = VRegisterFrom(locations->InAt(0)); in VisitVecAbs()
362 VRegister src = VRegisterFrom(locations->InAt(0)); in VisitVecNot()
413 VRegister lhs = VRegisterFrom(locations->InAt(0)); in VisitVecAdd()
414 VRegister rhs = VRegisterFrom(locations->InAt(1)); in VisitVecAdd()
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Dcommon_arm.h111 return SRegisterFrom(instr->GetLocations()->InAt(input_index)); in InputSRegisterAt()
117 return DRegisterFrom(instr->GetLocations()->InAt(input_index)); in InputDRegisterAt()
140 return RegisterFrom(instr->GetLocations()->InAt(input_index), in InputRegisterAt()
199 return OperandFrom(instr->GetLocations()->InAt(input_index), in InputOperandAt()
Dintrinsics_arm_vixl.cc191 Location dest_pos = locations->InAt(3); in EmitNativeCode()
274 Location input = locations->InAt(0); in MoveFPToInt()
284 Location input = locations->InAt(0); in MoveIntToFP()
347 Location in = locations->InAt(0); in GenNumberOfLeadingZeros()
395 vixl32::Register in_reg_lo = LowRegisterFrom(locations->InAt(0)); in GenNumberOfTrailingZeros()
396 vixl32::Register in_reg_hi = HighRegisterFrom(locations->InAt(0)); in GenNumberOfTrailingZeros()
409 vixl32::Register in = RegisterFrom(locations->InAt(0)); in GenNumberOfTrailingZeros()
510 __ Ldrsb(OutputRegister(invoke), MemOperand(LowRegisterFrom(invoke->GetLocations()->InAt(0)))); in VisitMemoryPeekByte()
520 __ Ldr(OutputRegister(invoke), MemOperand(LowRegisterFrom(invoke->GetLocations()->InAt(0)))); in VisitMemoryPeekIntNative()
530 vixl32::Register addr = LowRegisterFrom(invoke->GetLocations()->InAt(0)); in VisitMemoryPeekLongNative()
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Dssa_liveness_analysis.h146 Location location = GetUser()->GetLocations()->InAt(GetInputIndex()); in RequiresRegister()
333 } else if (!locations->InAt(input_index).IsValid()) {
964 && (locations->InAt(0).IsRegister() in DefinitionRequiresRegister()
965 || locations->InAt(0).IsRegisterPair() in DefinitionRequiresRegister()
966 || locations->InAt(0).GetPolicy() == Location::kRequiresRegister))) { in DefinitionRequiresRegister()
970 && (locations->InAt(0).IsFpuRegister() in DefinitionRequiresRegister()
971 || locations->InAt(0).IsFpuRegisterPair() in DefinitionRequiresRegister()
972 || locations->InAt(0).GetPolicy() == Location::kRequiresFpuRegister))) { in DefinitionRequiresRegister()
Dcommon_arm64.h86 return RegisterFrom(instr->GetLocations()->InAt(input_index), in InputRegisterAt()
125 return FPRegisterFrom(instr->GetLocations()->InAt(input_index), in InputFPRegisterAt()
172 return OperandFrom(instr->GetLocations()->InAt(input_index), in InputOperandAt()
Dssa_liveness_analysis.cc112 bool has_in_location = current->GetLocations()->InAt(i).IsValid(); in RecursivelyProcessInputs()
225 DCHECK(!user->GetLocations()->InAt(index).IsValid()); in ComputeLiveRanges()
418 Location expected = locations->InAt(use.GetInputIndex()); in FindFirstRegisterHint()
Dregister_allocation_resolver.cc133 if (locations->InAt(0).IsUnallocated()) { in Resolve()
136 DCHECK(locations->InAt(0).Equals(source)); in Resolve()
342 Location expected_location = locations->InAt(use.GetInputIndex()); in ConnectSiblings()
Dintrinsics.h93 Location actual_loc = locations->InAt(i); in INTRINSICS_LIST()
Dregister_allocator_linear_scan.cc291 Location input = locations->InAt(i); in ProcessInstruction()
346 Location first = locations->InAt(0); in ProcessInstruction()
640 if (locations->InAt(i).IsValid()) { in TryAllocateFreeReg()
Dcode_generator.cc110 DCHECK(CheckType(instruction->GetType(), locations->InAt(0))) in CheckTypeConsistency()
112 << " " << locations->InAt(0); in CheckTypeConsistency()
121 DCHECK(CheckType(inputs[i]->GetType(), locations->InAt(i))) in CheckTypeConsistency()
122 << inputs[i]->GetType() << " " << locations->InAt(i); in CheckTypeConsistency()
718 locations->InAt(is_instance ? 1 : 0), in GenerateUnresolvedFieldAccess()
Dlocations.h515 Location InAt(uint32_t at) const { in InAt() function
Dregister_allocator_graph_color.cc881 Location input = locations->InAt(i); in CheckForFixedInputs()
904 out = instruction->GetLocations()->InAt(0); in CheckForFixedOutput()
1437 Location input = locations->InAt(use.GetInputIndex()); in FindCoalesceOpportunities()
Dgraph_visualizer.cc655 DumpLocation(input_list.NewEntryStream(), locations->InAt(i)); in PrintInstruction()