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Searched refs:Out (Results 1 – 18 of 18) sorted by relevance

/art/compiler/optimizing/
Dcode_generator_vector_x86.cc64 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecReplicateScalar()
106 DCHECK(locations->InAt(0).Equals(locations->Out())); in VisitVecReplicateScalar()
111 DCHECK(locations->InAt(0).Equals(locations->Out())); in VisitVecReplicateScalar()
161 __ movd(locations->Out().AsRegister<Register>(), src); in VisitVecExtractScalar()
166 __ movd(locations->Out().AsRegisterPairLow<Register>(), src); in VisitVecExtractScalar()
168 __ movd(locations->Out().AsRegisterPairHigh<Register>(), tmp); in VisitVecExtractScalar()
175 DCHECK(locations->InAt(0).Equals(locations->Out())); // no code required in VisitVecExtractScalar()
218 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecReduce()
264 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecCnv()
282 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecNeg()
[all …]
Dcode_generator_vector_x86_64.cc59 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecReplicateScalar()
97 DCHECK(locations->InAt(0).Equals(locations->Out())); in VisitVecReplicateScalar()
102 DCHECK(locations->InAt(0).Equals(locations->Out())); in VisitVecReplicateScalar()
148 __ movd(locations->Out().AsRegister<CpuRegister>(), src, /*64-bit*/ false); in VisitVecExtractScalar()
152 __ movd(locations->Out().AsRegister<CpuRegister>(), src, /*64-bit*/ true); in VisitVecExtractScalar()
158 DCHECK(locations->InAt(0).Equals(locations->Out())); // no code required in VisitVecExtractScalar()
201 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecReduce()
247 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecCnv()
265 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecNeg()
316 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecAbs()
[all …]
Dcode_generator_vector_arm_vixl.cc56 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecReplicateScalar()
137 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecReduce()
174 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecNeg()
203 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecAbs()
230 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecNot()
278 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecAdd()
308 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecSaturationAdd()
340 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecHalvingAdd()
380 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecSub()
410 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecSaturationSub()
[all …]
Dcode_generator_vector_arm64.cc84 VRegister dst = VRegisterFrom(locations->Out()); in VisitVecReplicateScalar()
183 DCHECK(locations->InAt(0).Equals(locations->Out())); // no code required in VisitVecExtractScalar()
225 VRegister dst = DRegisterFrom(locations->Out()); in VisitVecReduce()
265 VRegister dst = VRegisterFrom(locations->Out()); in VisitVecCnv()
283 VRegister dst = VRegisterFrom(locations->Out()); in VisitVecNeg()
324 VRegister dst = VRegisterFrom(locations->Out()); in VisitVecAbs()
363 VRegister dst = VRegisterFrom(locations->Out()); in VisitVecNot()
415 VRegister dst = VRegisterFrom(locations->Out()); in VisitVecAdd()
457 VRegister dst = VRegisterFrom(locations->Out()); in VisitVecSaturationAdd()
489 VRegister dst = VRegisterFrom(locations->Out()); in VisitVecHalvingAdd()
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Dssa_liveness_analysis.cc55 if (locations != nullptr && locations->Out().IsValid()) { in NumberInstructions()
73 if (locations != nullptr && locations->Out().IsValid()) { in NumberInstructions()
113 bool has_out_location = input->GetLocations()->Out().IsValid(); in RecursivelyProcessInputs()
221 DCHECK(!current->GetLocations()->Out().IsValid()); in ComputeLiveRanges()
456 Location out = locations->Out(); in FindHintAtDefinition()
524 return defined_by->GetLocations()->Out(); in ToLocation()
Dintrinsics_utils.h65 Location out = invoke_->GetLocations()->Out(); in EmitNativeCode()
Dcommon_arm.h90 return SRegisterFrom(instr->GetLocations()->Out()); in OutputSRegister()
96 return DRegisterFrom(instr->GetLocations()->Out()); in OutputDRegister()
136 return RegisterFrom(instr->GetLocations()->Out(), instr->GetType()); in OutputRegister()
Dintrinsics_arm_vixl.cc103 Location out = invoke_->GetLocations()->Out(); in EmitNativeCode()
275 Location output = locations->Out(); in MoveFPToInt()
285 Location output = locations->Out(); in MoveIntToFP()
348 vixl32::Register out = RegisterFrom(locations->Out()); in GenNumberOfLeadingZeros()
392 vixl32::Register out = RegisterFrom(locations->Out()); in GenNumberOfTrailingZeros()
533 vixl32::Register lo = LowRegisterFrom(invoke->GetLocations()->Out()); in VisitMemoryPeekLongNative()
534 vixl32::Register hi = HighRegisterFrom(invoke->GetLocations()->Out()); in VisitMemoryPeekLongNative()
624 Location trg_loc = locations->Out(); in GenUnsafeGet()
2558 vixl32::Register out_reg_lo = LowRegisterFrom(locations->Out()); in VisitLongReverse()
2559 vixl32::Register out_reg_hi = HighRegisterFrom(locations->Out()); in VisitLongReverse()
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Dcommon_arm64.h82 return RegisterFrom(instr->GetLocations()->Out(), instr->GetType()); in OutputRegister()
121 return FPRegisterFrom(instr->GetLocations()->Out(), instr->GetType()); in OutputFPRegister()
Dcode_generator.cc108 if (locations->Out().IsUnallocated() in CheckTypeConsistency()
109 && (locations->Out().GetPolicy() == Location::kSameAsFirstInput)) { in CheckTypeConsistency()
114 DCHECK(CheckType(instruction->GetType(), locations->Out())) in CheckTypeConsistency()
116 << " " << locations->Out(); in CheckTypeConsistency()
768 MoveLocation(locations->Out(), calling_convention.GetReturnLocation(field_type), field_type); in GenerateUnresolvedFieldAccess()
1280 Location location = current_phi->GetLocations()->Out(); in RecordCatchBlockInfo()
Dregister_allocation_resolver.cc62 Location location = locations->Out(); in Resolve()
466 location_source = defined_by->GetLocations()->Out(); in ConnectSplitSiblings()
Dlocations.h567 Location Out() const { return output_; } in Out() function
Dregister_allocator_test.cc768 ASSERT_EQ(first_sub->GetLocations()->Out().GetPolicy(), Location::kSameAsFirstInput); in SameAsFirstInputHint()
769 ASSERT_EQ(second_sub->GetLocations()->Out().GetPolicy(), Location::kSameAsFirstInput); in SameAsFirstInputHint()
Dssa_liveness_analysis.h596 DCHECK(defined_by_->GetLocations()->Out().IsValid()); in FirstUseAfter()
957 Location location = locations->Out(); in DefinitionRequiresRegister()
Dregister_allocator_linear_scan.cc344 Location output = locations->Out(); in ProcessInstruction()
637 if (!locations->OutputCanOverlapWithInputs() && locations->Out().IsUnallocated()) { in TryAllocateFreeReg()
Dregister_allocator_graph_color.cc838 DCHECK(!locations->Out().IsValid()); in ProcessInstruction()
899 Location out = interval->GetDefinedBy()->GetLocations()->Out(); in CheckForFixedOutput()
1377 Location out = defined_by->GetLocations()->Out(); in FindCoalesceOpportunities()
Dgraph_visualizer.cc659 DumpLocation(attr, locations->Out()); in PrintInstruction()
/art/tools/dexfuzz/
DREADME85 |Iterations|VerifyFail|MutateFail|Timed Out |Successful|Divergence|
96 Timed Out - mutated files that timed out for one or more backends.