Searched refs:R4 (Results 1 – 6 of 6) sorted by relevance
| /art/compiler/utils/ |
| D | assembler_thumb_test.cc | 297 #define R4 vixl::aarch32::r4 macro
303 __ LoadFromOffset(kLoadWord, R2, R4, 12); in TEST_F()
304 __ LoadFromOffset(kLoadWord, R2, R4, 0xfff); in TEST_F()
305 __ LoadFromOffset(kLoadWord, R2, R4, 0x1000); in TEST_F()
306 __ LoadFromOffset(kLoadWord, R2, R4, 0x1000a4); in TEST_F()
307 __ LoadFromOffset(kLoadWord, R2, R4, 0x101000); in TEST_F()
308 __ LoadFromOffset(kLoadWord, R4, R4, 0x101000); in TEST_F()
309 __ LoadFromOffset(kLoadUnsignedHalfword, R2, R4, 12); in TEST_F()
310 __ LoadFromOffset(kLoadUnsignedHalfword, R2, R4, 0xfff); in TEST_F()
311 __ LoadFromOffset(kLoadUnsignedHalfword, R2, R4, 0x1000); in TEST_F()
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| /art/compiler/jni/quick/arm/ |
| D | calling_convention_arm.cc | 127 ArmManagedRegister::FromCoreRegister(R4),
536 return callee_save.Equals(ArmManagedRegister::FromCoreRegister(R4)); in HiddenArgumentRegister()
540 [](Register reg) { return reg == R4; })); in HiddenArgumentRegister()
541 DCHECK(!InterproceduralScratchRegister().Equals(ArmManagedRegister::FromCoreRegister(R4))); in HiddenArgumentRegister()
542 return ArmManagedRegister::FromCoreRegister(R4); in HiddenArgumentRegister()
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| /art/runtime/arch/arm/ |
| D | registers_arm.h | 31 R4 = 4, enumerator
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| D | callee_save_frame_arm.h | 39 (1 << art::arm::R4) | (1 << art::arm::R9);
42 (1 << art::arm::R4) | (1 << art::arm::R9) | (1 << art::arm::R12);
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| /art/compiler/optimizing/ |
| D | codegen_test_utils.h | 96 blocked_core_registers_[arm::R4] = true; in SetupBlockedRegisters()
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| /art/compiler/utils/arm/ |
| D | managed_register_arm_test.cc | 271 EXPECT_EQ(R4, reg.AsRegisterPairLow()); in TEST()
273 EXPECT_TRUE(reg.Equals(ArmManagedRegister::FromCoreRegisterPair(R4))); in TEST()
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