| /art/libelffile/dwarf/ |
| D | register.h | 24 class Reg {
26 explicit Reg(int reg_num) : num_(reg_num) { } in Reg() function
38 static Reg ArmCore(int num) { return Reg(num); } // R0-R15. in ArmCore()
39 static Reg ArmFp(int num) { return Reg(64 + num); } // S0–S31. in ArmFp()
40 static Reg ArmDp(int num) { return Reg(256 + num); } // D0–D31. in ArmDp()
41 static Reg Arm64Core(int num) { return Reg(num); } // X0-X31. in Arm64Core()
42 static Reg Arm64Fp(int num) { return Reg(64 + num); } // V0-V31. in Arm64Fp()
43 static Reg MipsCore(int num) { return Reg(num); } in MipsCore()
44 static Reg Mips64Core(int num) { return Reg(num); } in Mips64Core()
45 static Reg MipsFp(int num) { return Reg(32 + num); } in MipsFp()
[all …]
|
| D | debug_frame_opcode_writer.h | 73 void ALWAYS_INLINE RelOffset(Reg reg, int offset) { in RelOffset()
83 void ALWAYS_INLINE RelOffsetForMany(Reg reg_base, in RelOffsetForMany()
94 RelOffset(Reg(reg_base.num() + i), offset); in RelOffsetForMany()
101 void ALWAYS_INLINE RestoreMany(Reg reg_base, uint32_t reg_mask) { in RestoreMany()
108 Restore(Reg(reg_base.num() + i)); in RestoreMany()
119 void ALWAYS_INLINE Offset(Reg reg, int offset) { in Offset()
141 void ALWAYS_INLINE Restore(Reg reg) { in Restore()
153 void ALWAYS_INLINE Undefined(Reg reg) { in Undefined()
161 void ALWAYS_INLINE SameValue(Reg reg) { in SameValue()
170 void ALWAYS_INLINE Register(Reg reg, Reg new_reg) { in Register()
[all …]
|
| D | headers.h | 42 Reg return_address_register, in WriteCIE()
|
| /art/compiler/debug/ |
| D | elf_debug_frame_writer.h | 39 using Reg = dwarf::Reg; in WriteCIE() local
47 opcodes.DefCFA(Reg::ArmCore(13), 0); // R13(SP). in WriteCIE()
51 opcodes.Undefined(Reg::ArmCore(reg)); in WriteCIE()
53 opcodes.SameValue(Reg::ArmCore(reg)); in WriteCIE()
59 opcodes.Undefined(Reg::ArmFp(reg)); in WriteCIE()
61 opcodes.SameValue(Reg::ArmFp(reg)); in WriteCIE()
64 auto return_reg = Reg::ArmCore(14); // R14(LR). in WriteCIE()
70 opcodes.DefCFA(Reg::Arm64Core(31), 0); // R31(SP). in WriteCIE()
74 opcodes.Undefined(Reg::Arm64Core(reg)); in WriteCIE()
76 opcodes.SameValue(Reg::Arm64Core(reg)); in WriteCIE()
[all …]
|
| D | elf_debug_loc_writer.h | 32 using Reg = dwarf::Reg; variable
34 static Reg GetDwarfCoreReg(InstructionSet isa, int machine_reg) { in GetDwarfCoreReg()
38 return Reg::ArmCore(machine_reg); in GetDwarfCoreReg()
40 return Reg::Arm64Core(machine_reg); in GetDwarfCoreReg()
42 return Reg::X86Core(machine_reg); in GetDwarfCoreReg()
44 return Reg::X86_64Core(machine_reg); in GetDwarfCoreReg()
51 static Reg GetDwarfFpReg(InstructionSet isa, int machine_reg) { in GetDwarfFpReg()
55 return Reg::ArmFp(machine_reg); in GetDwarfFpReg()
57 return Reg::Arm64Fp(machine_reg); in GetDwarfFpReg()
59 return Reg::X86Fp(machine_reg); in GetDwarfFpReg()
[all …]
|
| /art/compiler/utils/ |
| D | assembler_test.h | 52 typename Reg,
77 std::string RepeatR(void (Ass::*f)(Reg), const std::string& fmt) { in RepeatR() argument
78 return RepeatTemplatedRegister<Reg>(f, in RepeatR()
84 std::string Repeatr(void (Ass::*f)(Reg), const std::string& fmt) { in Repeatr() argument
85 return RepeatTemplatedRegister<Reg>(f, in Repeatr()
91 std::string RepeatRR(void (Ass::*f)(Reg, Reg), const std::string& fmt) { in RepeatRR() argument
92 return RepeatTemplatedRegisters<Reg, Reg>(f, in RepeatRR()
100 std::string RepeatRRNoDupes(void (Ass::*f)(Reg, Reg), const std::string& fmt) { in RepeatRRNoDupes() argument
101 return RepeatTemplatedRegistersNoDupes<Reg, Reg>(f, in RepeatRRNoDupes()
109 std::string Repeatrr(void (Ass::*f)(Reg, Reg), const std::string& fmt) { in Repeatrr() argument
[all …]
|
| /art/compiler/debug/dwarf/ |
| D | dwarf_test.cc | 40 const Reg reg(6); in TEST_F()
75 opcodes.Offset(Reg(0x3F), -offset); in TEST_F()
77 opcodes.Offset(Reg(0x40), -offset); in TEST_F()
79 opcodes.Offset(Reg(0x40), offset); in TEST_F()
85 opcodes.Register(reg, Reg(1)); in TEST_F()
91 opcodes.Restore(Reg(0x3F)); in TEST_F()
93 opcodes.Restore(Reg(0x40)); in TEST_F()
105 opcodes.DefCFA(Reg(4), 100); // ESP in TEST_F()
109 opcodes.RelOffset(Reg(0), 0); // push R0 in TEST_F()
111 opcodes.RelOffset(Reg(1), 4); // push R1 in TEST_F()
[all …]
|
| /art/compiler/utils/arm64/ |
| D | assembler_arm64.h | 46 static inline dwarf::Reg DWARFReg(vixl::aarch64::CPURegister reg) { in DWARFReg()
48 return dwarf::Reg::Arm64Fp(reg.GetCode()); in DWARFReg()
51 return dwarf::Reg::Arm64Core(reg.GetCode()); in DWARFReg()
|
| /art/compiler/utils/arm/ |
| D | assembler_arm_vixl.h | 43 inline dwarf::Reg DWARFReg(vixl32::Register reg) { in DWARFReg()
44 return dwarf::Reg::ArmCore(static_cast<int>(reg.GetCode())); in DWARFReg()
47 inline dwarf::Reg DWARFReg(vixl32::SRegister reg) { in DWARFReg()
48 return dwarf::Reg::ArmFp(static_cast<int>(reg.GetCode())); in DWARFReg()
|
| /art/compiler/ |
| D | cfi_test.h | 51 dwarf::WriteCIE(is64bit, dwarf::Reg(8), initial_opcodes, &debug_frame_data_); in GenerateExpected()
|
| /art/compiler/utils/x86_64/ |
| D | jni_macro_assembler_x86_64.cc | 27 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg()
28 return dwarf::Reg::X86_64Core(static_cast<int>(reg)); in DWARFReg()
30 static dwarf::Reg DWARFReg(FloatRegister reg) { in DWARFReg()
31 return dwarf::Reg::X86_64Fp(static_cast<int>(reg)); in DWARFReg()
|
| /art/compiler/utils/x86/ |
| D | jni_macro_assembler_x86.cc | 36 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg()
37 return dwarf::Reg::X86Core(static_cast<int>(reg)); in DWARFReg()
|