| /art/compiler/utils/ |
| D | assembler_thumb_test.cc | 178 #define __ assembler-> macro
182 __ FinalizeCode(); in EmitAndCheck()
183 size_t cs = __ CodeSize(); in EmitAndCheck()
186 __ FinalizeInstructions(code); in EmitAndCheck()
199 #undef __
201 #define __ assembler. macro
229 __ BuildFrame(frame_size, mr_conv->MethodRegister(), callee_save_regs, mr_conv->EntrySpills()); in TEST_F()
230 __ IncreaseFrameSize(32); in TEST_F()
233 __ IncreaseFrameSize(4096); in TEST_F()
234 __ Load(method_register, FrameOffset(32), 4); in TEST_F()
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| /art/compiler/utils/x86/ |
| D | jni_macro_assembler_x86.cc | 45 #define __ asm_. macro
65 __ pushl(spill); in BuildFrame()
76 __ addl(ESP, Immediate(-adjust)); in BuildFrame()
80 __ pushl(method_reg.AsX86().AsCpuRegister()); in BuildFrame()
88 __ movl(Address(ESP, offset), spill.AsX86().AsCpuRegister()); in BuildFrame()
92 __ movsd(Address(ESP, frame_size + spill.getSpillOffset()), spill.AsX86().AsXmmRegister()); in BuildFrame()
95 __ movss(Address(ESP, frame_size + spill.getSpillOffset()), spill.AsX86().AsXmmRegister()); in BuildFrame()
109 __ addl(ESP, Immediate(adjust)); in RemoveFrame()
114 __ popl(spill); in RemoveFrame()
118 __ ret(); in RemoveFrame()
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| /art/compiler/utils/x86_64/ |
| D | jni_macro_assembler_x86_64.cc | 39 #define __ asm_. macro
57 __ pushq(spill.AsCpuRegister()); in BuildFrame()
68 __ subq(CpuRegister(RSP), Immediate(rest_of_frame)); in BuildFrame()
78 __ movsd(Address(CpuRegister(RSP), offset), spill.AsXmmRegister()); in BuildFrame()
87 __ movq(Address(CpuRegister(RSP), 0), method_reg.AsX86_64().AsCpuRegister()); in BuildFrame()
93 __ movq(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), in BuildFrame()
97 __ movl(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), in BuildFrame()
102 __ movsd(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), in BuildFrame()
106 __ movss(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), in BuildFrame()
126 __ movsd(spill.AsXmmRegister(), Address(CpuRegister(RSP), offset)); in RemoveFrame()
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| /art/compiler/optimizing/ |
| D | intrinsics_arm_vixl.cc | 37 #define __ assembler->GetVIXLAssembler()-> macro
90 __ Bind(GetEntryLabel()); in EmitNativeCode()
111 __ B(GetExitLabel()); in EmitNativeCode()
139 __ Add(base, array, element_size * constant + data_offset); in GenSystemArrayCopyBaseAddress()
141 __ Add(base, array, Operand(RegisterFrom(pos), vixl32::LSL, element_size_shift)); in GenSystemArrayCopyBaseAddress()
142 __ Add(base, base, data_offset); in GenSystemArrayCopyBaseAddress()
161 __ Add(end, base, element_size * constant); in GenSystemArrayCopyEndAddress()
163 __ Add(end, base, Operand(RegisterFrom(copy_length), vixl32::LSL, element_size_shift)); in GenSystemArrayCopyEndAddress()
197 __ Bind(GetEntryLabel()); in EmitNativeCode()
202 __ Bind(&loop); in EmitNativeCode()
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| D | code_generator_vector_x86.cc | 26 #define __ down_cast<X86Assembler*>(GetAssembler())-> // NOLINT macro
69 cpu_has_avx ? __ vxorps(dst, dst, dst) : __ xorps(dst, dst); in VisitVecReplicateScalar()
78 __ movd(dst, locations->InAt(0).AsRegister<Register>()); in VisitVecReplicateScalar()
79 __ punpcklbw(dst, dst); in VisitVecReplicateScalar()
80 __ punpcklwd(dst, dst); in VisitVecReplicateScalar()
81 __ pshufd(dst, dst, Immediate(0)); in VisitVecReplicateScalar()
86 __ movd(dst, locations->InAt(0).AsRegister<Register>()); in VisitVecReplicateScalar()
87 __ punpcklwd(dst, dst); in VisitVecReplicateScalar()
88 __ pshufd(dst, dst, Immediate(0)); in VisitVecReplicateScalar()
92 __ movd(dst, locations->InAt(0).AsRegister<Register>()); in VisitVecReplicateScalar()
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| D | code_generator_vector_x86_64.cc | 26 #define __ down_cast<X86_64Assembler*>(GetAssembler())-> // NOLINT macro
64 cpu_has_avx ? __ vxorps(dst, dst, dst) : __ xorps(dst, dst); in VisitVecReplicateScalar()
73 __ movd(dst, locations->InAt(0).AsRegister<CpuRegister>(), /*64-bit*/ false); in VisitVecReplicateScalar()
74 __ punpcklbw(dst, dst); in VisitVecReplicateScalar()
75 __ punpcklwd(dst, dst); in VisitVecReplicateScalar()
76 __ pshufd(dst, dst, Immediate(0)); in VisitVecReplicateScalar()
81 __ movd(dst, locations->InAt(0).AsRegister<CpuRegister>(), /*64-bit*/ false); in VisitVecReplicateScalar()
82 __ punpcklwd(dst, dst); in VisitVecReplicateScalar()
83 __ pshufd(dst, dst, Immediate(0)); in VisitVecReplicateScalar()
87 __ movd(dst, locations->InAt(0).AsRegister<CpuRegister>(), /*64-bit*/ false); in VisitVecReplicateScalar()
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| D | code_generator_vector_arm64.cc | 39 #define __ GetVIXLAssembler()-> macro
91 __ Movi(dst.V16B(), Int64FromLocation(src_loc)); in VisitVecReplicateScalar()
93 __ Dup(dst.V16B(), InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar()
100 __ Movi(dst.V8H(), Int64FromLocation(src_loc)); in VisitVecReplicateScalar()
102 __ Dup(dst.V8H(), InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar()
108 __ Movi(dst.V4S(), Int64FromLocation(src_loc)); in VisitVecReplicateScalar()
110 __ Dup(dst.V4S(), InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar()
116 __ Movi(dst.V2D(), Int64FromLocation(src_loc)); in VisitVecReplicateScalar()
118 __ Dup(dst.V2D(), XRegisterFrom(src_loc)); in VisitVecReplicateScalar()
124 __ Fmov(dst.V4S(), src_loc.GetConstant()->AsFloatConstant()->GetValue()); in VisitVecReplicateScalar()
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| D | code_generator_vector_arm_vixl.cc | 34 #define __ GetVIXLAssembler()-> macro
62 __ Vdup(Untyped8, dst, InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar()
67 __ Vdup(Untyped16, dst, InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar()
71 __ Vdup(Untyped32, dst, InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar()
98 __ Vmov(OutputRegister(instruction), DRegisterLane(src, 0)); in VisitVecExtractScalar()
143 __ Vpadd(DataTypeValue::I32, dst, src, src); in VisitVecReduce()
146 __ Vpmin(DataTypeValue::S32, dst, src, src); in VisitVecReduce()
149 __ Vpmax(DataTypeValue::S32, dst, src, src); in VisitVecReduce()
179 __ Vneg(DataTypeValue::S8, dst, src); in VisitVecNeg()
184 __ Vneg(DataTypeValue::S16, dst, src); in VisitVecNeg()
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| D | optimizing_cfi_test.cc | 193 #define __ down_cast<arm::ArmVIXLAssembler*>(GetCodeGenerator() \ in TEST_ISA() macro
196 __ CompareAndBranchIfZero(r0, &target); in TEST_ISA()
199 __ Ldr(r0, vixl32::MemOperand(r0)); in TEST_ISA()
201 __ Bind(&target); in TEST_ISA()
202 #undef __ in TEST_ISA()
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| /art/compiler/jni/quick/ |
| D | jni_compiler.cc | 48 #define __ jni_asm-> macro
227 __ BuildFrame(current_frame_size, method_register, callee_save_regs, mr_conv->EntrySpills()); in ArtJniCompileMethodInternal()
237 __ StoreImmediateToFrame(main_jni_conv->HandleScopeNumRefsOffset(), in ArtJniCompileMethodInternal()
241 __ CopyRawPtrFromThread(main_jni_conv->HandleScopeLinkOffset(), in ArtJniCompileMethodInternal()
244 __ StoreStackOffsetToThread(Thread::TopHandleScopeOffset<kPointerSize>(), in ArtJniCompileMethodInternal()
259 __ LoadRef(main_jni_conv->InterproceduralScratchRegister(), in ArtJniCompileMethodInternal()
261 __ VerifyObject(main_jni_conv->InterproceduralScratchRegister(), false); in ArtJniCompileMethodInternal()
263 __ StoreRef(handle_scope_offset, main_jni_conv->InterproceduralScratchRegister()); in ArtJniCompileMethodInternal()
286 __ VerifyObject(in_reg, mr_conv->IsCurrentArgPossiblyNull()); in ArtJniCompileMethodInternal()
287 __ StoreRef(handle_scope_offset, in_reg); in ArtJniCompileMethodInternal()
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| /art/runtime/hprof/ |
| D | hprof.cc | 433 #define __ output_-> macro
569 __ AddU4(sn); in WriteClassTable()
570 __ AddObjectId(c); in WriteClassTable()
571 __ AddStackTraceSerialNumber(LookupStackTraceSerialNumber(c)); in WriteClassTable()
572 __ AddStringId(LookupClassNameId(c)); in WriteClassTable()
587 __ AddU4(id); in WriteStringTable()
588 __ AddUtf8String(string.c_str()); in WriteStringTable()
664 __ AddU1List(reinterpret_cast<const uint8_t*>(magic), sizeof(magic)); in WriteFixedHeader()
671 __ AddU4(sizeof(uint32_t)); in WriteFixedHeader()
679 __ AddU4(static_cast<uint32_t>(nowMs >> 32)); in WriteFixedHeader()
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| /art/compiler/trampolines/ |
| D | trampoline_compiler.cc | 39 #define __ assembler. macro
77 __ FinalizeCode(); in CreateTrampoline()
78 size_t cs = __ CodeSize(); in CreateTrampoline()
81 __ FinalizeInstructions(code); in CreateTrampoline()
99 __ JumpTo(Arm64ManagedRegister::FromXRegister(X0), Offset(offset.Int32Value()), in CreateTrampoline()
104 __ LoadRawPtr(Arm64ManagedRegister::FromXRegister(IP1), in CreateTrampoline()
108 __ JumpTo(Arm64ManagedRegister::FromXRegister(IP1), Offset(offset.Int32Value()), in CreateTrampoline()
113 __ JumpTo(Arm64ManagedRegister::FromXRegister(TR), Offset(offset.Int32Value()), in CreateTrampoline()
119 __ FinalizeCode(); in CreateTrampoline()
120 size_t cs = __ CodeSize(); in CreateTrampoline()
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| /art/runtime/ |
| D | runtime_intrinsics.cc | 70 #define SETUP_INTRINSICS(Name, InvokeType, _, __, ___, ClassName, MethodName, Signature) \ in InitializeIntrinsics() argument
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| D | method_handles.cc | 81 #define CASE_PRIMITIVE(primitive, _, java_name, __) \ in GetBoxedPrimitiveClass() argument
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| /art/build/ |
| D | Android.cpplint.mk | 55 art_cpplint_touch := $$(OUT_CPPLINT)/$$(subst /,__,$$(art_cpplint_file))
|