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Searched refs:vixl32 (Results 1 – 10 of 10) sorted by relevance

/art/compiler/utils/arm/
Dassembler_arm_vixl.h38 namespace vixl32 = vixl::aarch32; variable
43 inline dwarf::Reg DWARFReg(vixl32::Register reg) { in DWARFReg()
47 inline dwarf::Reg DWARFReg(vixl32::SRegister reg) { in DWARFReg()
51 class ArmVIXLMacroAssembler final : public vixl32::MacroAssembler {
58 : vixl32::MacroAssembler(ArmVIXLMacroAssembler::kDefaultCodeBufferCapacity) {} in ArmVIXLMacroAssembler()
69 void CompareAndBranchIfZero(vixl32::Register rn,
70 vixl32::Label* label,
72 void CompareAndBranchIfNonZero(vixl32::Register rn,
73 vixl32::Label* label,
86 void (func_name)(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { \
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Dassembler_arm_vixl.cc39 extern const vixl32::Register tr(TR);
41 extern const vixl32::Register mr(MR);
71 void ArmVIXLAssembler::MaybePoisonHeapReference(vixl32::Register reg) { in MaybePoisonHeapReference()
77 void ArmVIXLAssembler::MaybeUnpoisonHeapReference(vixl32::Register reg) { in MaybeUnpoisonHeapReference()
83 void ArmVIXLAssembler::GenerateMarkingRegisterCheck(vixl32::Register temp, int code) { in GenerateMarkingRegisterCheck()
88 vixl32::Label mr_is_ok; in GenerateMarkingRegisterCheck()
99 void ArmVIXLAssembler::LoadImmediate(vixl32::Register rd, int32_t value) { in LoadImmediate()
148 vixl32::Register temp, in AdjustLoadStoreOffset()
149 vixl32::Register base, in AdjustLoadStoreOffset()
245 vixl32::Register reg, in StoreToOffset()
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Djni_macro_assembler_arm_vixl.h208 void Load(ArmManagedRegister dest, vixl32::Register base, int32_t offset, size_t size);
216 vixl32::Label* Entry() { return &exception_entry_; } in Entry()
224 vixl32::Label exception_entry_;
239 vixl32::Label,
242 vixl32::Label* AsArm() { in AsArm()
Djni_macro_assembler_arm_vixl.cc26 namespace vixl32 = vixl::aarch32;
110 ___ Vpush(SRegisterList(vixl32::SRegister(first), POPCOUNT(fp_spill_mask))); in BuildFrame()
175 ___ Vpop(SRegisterList(vixl32::SRegister(first), POPCOUNT(fp_spill_mask))); in RemoveFrame()
202 vixl32::Register temp = temps.Acquire(); in RemoveFrame()
213 ___ Bx(vixl32::lr); in RemoveFrame()
515 3 * vixl32::kMaxInstructionSizeInBytes, in CreateHandleScopeEntry()
522 2 * vixl32::kMaxInstructionSizeInBytes, in CreateHandleScopeEntry()
552 2 * vixl32::kMaxInstructionSizeInBytes, in CreateHandleScopeEntry()
645 vixl32::Label* label = exception_blocks_.back()->Entry(); in ExceptionPoll()
700 vixl32::Register temp = temps.Acquire(); in EmitExceptionPoll()
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/art/compiler/optimizing/
Dintrinsics_arm_vixl.cc126 const vixl32::Register& array, in GenSystemArrayCopyBaseAddress()
128 const vixl32::Register& base) { in GenSystemArrayCopyBaseAddress()
141 __ Add(base, array, Operand(RegisterFrom(pos), vixl32::LSL, element_size_shift)); in GenSystemArrayCopyBaseAddress()
150 const vixl32::Register& base, in GenSystemArrayCopyEndAddress()
151 const vixl32::Register& end) { in GenSystemArrayCopyEndAddress()
163 __ Add(end, base, Operand(RegisterFrom(copy_length), vixl32::LSL, element_size_shift)); in GenSystemArrayCopyEndAddress()
190 vixl32::Register dest = InputRegisterAt(instruction_, 2); in EmitNativeCode()
192 vixl32::Register src_curr_addr = RegisterFrom(locations->GetTemp(0)); in EmitNativeCode()
193 vixl32::Register dst_curr_addr = RegisterFrom(locations->GetTemp(1)); in EmitNativeCode()
194 vixl32::Register src_stop_addr = RegisterFrom(locations->GetTemp(2)); in EmitNativeCode()
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Dcode_generator_vector_arm_vixl.cc20 namespace vixl32 = vixl::aarch32;
21 using namespace vixl32; // NOLINT(build/namespaces)
56 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecReplicateScalar()
94 vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); in VisitVecExtractScalar()
136 vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); in VisitVecReduce()
137 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecReduce()
173 vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); in VisitVecNeg()
174 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecNeg()
202 vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); in VisitVecAbs()
203 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecAbs()
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Doptimizing_cfi_test.cc33 namespace vixl32 = vixl::aarch32;
185 using vixl32::r0; in TEST_ISA()
195 vixl32::Label target; in TEST_ISA()
199 __ Ldr(r0, vixl32::MemOperand(r0)); in TEST_ISA()
Dcode_generator_arm_vixl.h128 VIXLInt32Literal *lit = new VIXLInt32Literal(0, vixl32::RawLiteral::kManuallyPlaced); in JumpTableARMVIXL()
253 void Exchange(vixl32::Register reg, int mem);
327 vixl32::Register class_reg);
413 /*out*/ vixl32::Register* scratch);
418 /*out*/ vixl32::Register* scratch);
520 vixl32::Label* GetFinalLabel(HInstruction* instruction, vixl32::Label* final_label);
748 vixl::aarch32::Register temp = vixl32::Register());
759 void MaybeGenerateInlineCacheCheck(HInstruction* instruction, vixl32::Register klass);
Dscheduler_arm.cc334 SBC, High32Bits(value + 1), vixl32::FlagsUpdate::SetFlags)) { in CanGenerateTest()
338 SBC, High32Bits(value), vixl32::FlagsUpdate::SetFlags)) { in CanGenerateTest()
/art/test/642-fp-callees/
Dinfo.txt1 Regression test for vixl32 backend, which used to incorrectly