1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __CONTEXT_H__ 8 #define __CONTEXT_H__ 9 10 /******************************************************************************* 11 * Constants that allow assembler code to access members of and the 'gp_regs' 12 * structure at their correct offsets. 13 ******************************************************************************/ 14 #define CTX_GPREGS_OFFSET U(0x0) 15 #define CTX_GPREG_X0 U(0x0) 16 #define CTX_GPREG_X1 U(0x8) 17 #define CTX_GPREG_X2 U(0x10) 18 #define CTX_GPREG_X3 U(0x18) 19 #define CTX_GPREG_X4 U(0x20) 20 #define CTX_GPREG_X5 U(0x28) 21 #define CTX_GPREG_X6 U(0x30) 22 #define CTX_GPREG_X7 U(0x38) 23 #define CTX_GPREG_X8 U(0x40) 24 #define CTX_GPREG_X9 U(0x48) 25 #define CTX_GPREG_X10 U(0x50) 26 #define CTX_GPREG_X11 U(0x58) 27 #define CTX_GPREG_X12 U(0x60) 28 #define CTX_GPREG_X13 U(0x68) 29 #define CTX_GPREG_X14 U(0x70) 30 #define CTX_GPREG_X15 U(0x78) 31 #define CTX_GPREG_X16 U(0x80) 32 #define CTX_GPREG_X17 U(0x88) 33 #define CTX_GPREG_X18 U(0x90) 34 #define CTX_GPREG_X19 U(0x98) 35 #define CTX_GPREG_X20 U(0xa0) 36 #define CTX_GPREG_X21 U(0xa8) 37 #define CTX_GPREG_X22 U(0xb0) 38 #define CTX_GPREG_X23 U(0xb8) 39 #define CTX_GPREG_X24 U(0xc0) 40 #define CTX_GPREG_X25 U(0xc8) 41 #define CTX_GPREG_X26 U(0xd0) 42 #define CTX_GPREG_X27 U(0xd8) 43 #define CTX_GPREG_X28 U(0xe0) 44 #define CTX_GPREG_X29 U(0xe8) 45 #define CTX_GPREG_LR U(0xf0) 46 #define CTX_GPREG_SP_EL0 U(0xf8) 47 #define CTX_GPREGS_END U(0x100) 48 49 /******************************************************************************* 50 * Constants that allow assembler code to access members of and the 'el3_state' 51 * structure at their correct offsets. Note that some of the registers are only 52 * 32-bits wide but are stored as 64-bit values for convenience 53 ******************************************************************************/ 54 #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) 55 #define CTX_SCR_EL3 U(0x0) 56 #define CTX_RUNTIME_SP U(0x8) 57 #define CTX_SPSR_EL3 U(0x10) 58 #define CTX_ELR_EL3 U(0x18) 59 #define CTX_EL3STATE_END U(0x20) 60 61 /******************************************************************************* 62 * Constants that allow assembler code to access members of and the 63 * 'el1_sys_regs' structure at their correct offsets. Note that some of the 64 * registers are only 32-bits wide but are stored as 64-bit values for 65 * convenience 66 ******************************************************************************/ 67 #define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) 68 #define CTX_SPSR_EL1 U(0x0) 69 #define CTX_ELR_EL1 U(0x8) 70 #define CTX_SCTLR_EL1 U(0x10) 71 #define CTX_ACTLR_EL1 U(0x18) 72 #define CTX_CPACR_EL1 U(0x20) 73 #define CTX_CSSELR_EL1 U(0x28) 74 #define CTX_SP_EL1 U(0x30) 75 #define CTX_ESR_EL1 U(0x38) 76 #define CTX_TTBR0_EL1 U(0x40) 77 #define CTX_TTBR1_EL1 U(0x48) 78 #define CTX_MAIR_EL1 U(0x50) 79 #define CTX_AMAIR_EL1 U(0x58) 80 #define CTX_TCR_EL1 U(0x60) 81 #define CTX_TPIDR_EL1 U(0x68) 82 #define CTX_TPIDR_EL0 U(0x70) 83 #define CTX_TPIDRRO_EL0 U(0x78) 84 #define CTX_PAR_EL1 U(0x80) 85 #define CTX_FAR_EL1 U(0x88) 86 #define CTX_AFSR0_EL1 U(0x90) 87 #define CTX_AFSR1_EL1 U(0x98) 88 #define CTX_CONTEXTIDR_EL1 U(0xa0) 89 #define CTX_VBAR_EL1 U(0xa8) 90 #define CTX_PMCR_EL0 U(0xb0) 91 92 /* 93 * If the platform is AArch64-only, there is no need to save and restore these 94 * AArch32 registers. 95 */ 96 #if CTX_INCLUDE_AARCH32_REGS 97 #define CTX_SPSR_ABT U(0xc0) /* Align to the next 16 byte boundary */ 98 #define CTX_SPSR_UND U(0xc8) 99 #define CTX_SPSR_IRQ U(0xd0) 100 #define CTX_SPSR_FIQ U(0xd8) 101 #define CTX_DACR32_EL2 U(0xe0) 102 #define CTX_IFSR32_EL2 U(0xe8) 103 #define CTX_FP_FPEXC32_EL2 U(0xf0) 104 #define CTX_TIMER_SYSREGS_OFF U(0x100) /* Align to the next 16 byte boundary */ 105 #else 106 #define CTX_TIMER_SYSREGS_OFF U(0xc0) /* Align to the next 16 byte boundary */ 107 #endif /* __CTX_INCLUDE_AARCH32_REGS__ */ 108 109 /* 110 * If the timer registers aren't saved and restored, we don't have to reserve 111 * space for them in the context 112 */ 113 #if NS_TIMER_SWITCH 114 #define CTX_CNTP_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x0)) 115 #define CTX_CNTP_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x8)) 116 #define CTX_CNTV_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x10)) 117 #define CTX_CNTV_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x18)) 118 #define CTX_CNTKCTL_EL1 (CTX_TIMER_SYSREGS_OFF + U(0x20)) 119 #define CTX_SYSREGS_END (CTX_TIMER_SYSREGS_OFF + U(0x30)) /* Align to the next 16 byte boundary */ 120 #else 121 #define CTX_SYSREGS_END CTX_TIMER_SYSREGS_OFF 122 #endif /* __NS_TIMER_SWITCH__ */ 123 124 /******************************************************************************* 125 * Constants that allow assembler code to access members of and the 'fp_regs' 126 * structure at their correct offsets. 127 ******************************************************************************/ 128 #if CTX_INCLUDE_FPREGS 129 #define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END) 130 #define CTX_FP_Q0 U(0x0) 131 #define CTX_FP_Q1 U(0x10) 132 #define CTX_FP_Q2 U(0x20) 133 #define CTX_FP_Q3 U(0x30) 134 #define CTX_FP_Q4 U(0x40) 135 #define CTX_FP_Q5 U(0x50) 136 #define CTX_FP_Q6 U(0x60) 137 #define CTX_FP_Q7 U(0x70) 138 #define CTX_FP_Q8 U(0x80) 139 #define CTX_FP_Q9 U(0x90) 140 #define CTX_FP_Q10 U(0xa0) 141 #define CTX_FP_Q11 U(0xb0) 142 #define CTX_FP_Q12 U(0xc0) 143 #define CTX_FP_Q13 U(0xd0) 144 #define CTX_FP_Q14 U(0xe0) 145 #define CTX_FP_Q15 U(0xf0) 146 #define CTX_FP_Q16 U(0x100) 147 #define CTX_FP_Q17 U(0x110) 148 #define CTX_FP_Q18 U(0x120) 149 #define CTX_FP_Q19 U(0x130) 150 #define CTX_FP_Q20 U(0x140) 151 #define CTX_FP_Q21 U(0x150) 152 #define CTX_FP_Q22 U(0x160) 153 #define CTX_FP_Q23 U(0x170) 154 #define CTX_FP_Q24 U(0x180) 155 #define CTX_FP_Q25 U(0x190) 156 #define CTX_FP_Q26 U(0x1a0) 157 #define CTX_FP_Q27 U(0x1b0) 158 #define CTX_FP_Q28 U(0x1c0) 159 #define CTX_FP_Q29 U(0x1d0) 160 #define CTX_FP_Q30 U(0x1e0) 161 #define CTX_FP_Q31 U(0x1f0) 162 #define CTX_FP_FPSR U(0x200) 163 #define CTX_FP_FPCR U(0x208) 164 #define CTX_FPREGS_END U(0x210) 165 #endif 166 167 #ifndef __ASSEMBLY__ 168 169 #include <cassert.h> 170 #include <platform_def.h> /* for CACHE_WRITEBACK_GRANULE */ 171 #include <stdint.h> 172 173 /* 174 * Common constants to help define the 'cpu_context' structure and its 175 * members below. 176 */ 177 #define DWORD_SHIFT U(3) 178 #define DEFINE_REG_STRUCT(name, num_regs) \ 179 typedef struct name { \ 180 uint64_t _regs[num_regs]; \ 181 } __aligned(16) name##_t 182 183 /* Constants to determine the size of individual context structures */ 184 #define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) 185 #define CTX_SYSREG_ALL (CTX_SYSREGS_END >> DWORD_SHIFT) 186 #if CTX_INCLUDE_FPREGS 187 #define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) 188 #endif 189 #define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) 190 191 /* 192 * AArch64 general purpose register context structure. Usually x0-x18, 193 * lr are saved as the compiler is expected to preserve the remaining 194 * callee saved registers if used by the C runtime and the assembler 195 * does not touch the remaining. But in case of world switch during 196 * exception handling, we need to save the callee registers too. 197 */ 198 DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); 199 200 /* 201 * AArch64 EL1 system register context structure for preserving the 202 * architectural state during switches from one security state to 203 * another in EL1. 204 */ 205 DEFINE_REG_STRUCT(el1_sys_regs, CTX_SYSREG_ALL); 206 207 /* 208 * AArch64 floating point register context structure for preserving 209 * the floating point state during switches from one security state to 210 * another. 211 */ 212 #if CTX_INCLUDE_FPREGS 213 DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL); 214 #endif 215 216 /* 217 * Miscellaneous registers used by EL3 firmware to maintain its state 218 * across exception entries and exits 219 */ 220 DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); 221 222 /* 223 * Macros to access members of any of the above structures using their 224 * offsets 225 */ 226 #define read_ctx_reg(ctx, offset) ((ctx)->_regs[offset >> DWORD_SHIFT]) 227 #define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[offset >> DWORD_SHIFT]) \ 228 = val) 229 230 /* 231 * Top-level context structure which is used by EL3 firmware to 232 * preserve the state of a core at EL1 in one of the two security 233 * states and save enough EL3 meta data to be able to return to that 234 * EL and security state. The context management library will be used 235 * to ensure that SP_EL3 always points to an instance of this 236 * structure at exception entry and exit. Each instance will 237 * correspond to either the secure or the non-secure state. 238 */ 239 typedef struct cpu_context { 240 gp_regs_t gpregs_ctx; 241 el3_state_t el3state_ctx; 242 el1_sys_regs_t sysregs_ctx; 243 #if CTX_INCLUDE_FPREGS 244 fp_regs_t fpregs_ctx; 245 #endif 246 } cpu_context_t; 247 248 /* Macros to access members of the 'cpu_context_t' structure */ 249 #define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) 250 #if CTX_INCLUDE_FPREGS 251 #define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx) 252 #endif 253 #define get_sysregs_ctx(h) (&((cpu_context_t *) h)->sysregs_ctx) 254 #define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx) 255 256 /* 257 * Compile time assertions related to the 'cpu_context' structure to 258 * ensure that the assembler and the compiler view of the offsets of 259 * the structure members is the same. 260 */ 261 CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \ 262 assert_core_context_gp_offset_mismatch); 263 CASSERT(CTX_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, sysregs_ctx), \ 264 assert_core_context_sys_offset_mismatch); 265 #if CTX_INCLUDE_FPREGS 266 CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \ 267 assert_core_context_fp_offset_mismatch); 268 #endif 269 CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), \ 270 assert_core_context_el3state_offset_mismatch); 271 272 /* 273 * Helper macro to set the general purpose registers that correspond to 274 * parameters in an aapcs_64 call i.e. x0-x7 275 */ 276 #define set_aapcs_args0(ctx, x0) do { \ 277 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \ 278 } while (0) 279 #define set_aapcs_args1(ctx, x0, x1) do { \ 280 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \ 281 set_aapcs_args0(ctx, x0); \ 282 } while (0) 283 #define set_aapcs_args2(ctx, x0, x1, x2) do { \ 284 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \ 285 set_aapcs_args1(ctx, x0, x1); \ 286 } while (0) 287 #define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \ 288 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \ 289 set_aapcs_args2(ctx, x0, x1, x2); \ 290 } while (0) 291 #define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \ 292 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \ 293 set_aapcs_args3(ctx, x0, x1, x2, x3); \ 294 } while (0) 295 #define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ 296 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \ 297 set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \ 298 } while (0) 299 #define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ 300 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \ 301 set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \ 302 } while (0) 303 #define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ 304 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \ 305 set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \ 306 } while (0) 307 308 /******************************************************************************* 309 * Function prototypes 310 ******************************************************************************/ 311 void el1_sysregs_context_save(el1_sys_regs_t *regs); 312 void el1_sysregs_context_save_post_ops(void); 313 void el1_sysregs_context_restore(el1_sys_regs_t *regs); 314 #if CTX_INCLUDE_FPREGS 315 void fpregs_context_save(fp_regs_t *regs); 316 void fpregs_context_restore(fp_regs_t *regs); 317 #endif 318 319 320 #undef CTX_SYSREG_ALL 321 #if CTX_INCLUDE_FPREGS 322 #undef CTX_FPREG_ALL 323 #endif 324 #undef CTX_GPREG_ALL 325 #undef CTX_EL3STATE_ALL 326 327 #endif /* __ASSEMBLY__ */ 328 329 #endif /* __CONTEXT_H__ */ 330