Searched refs:DDR_PCTL_BASE (Results 1 – 3 of 3) sorted by relevance
249 p_ddr_reg->pctladdr = DDR_PCTL_BASE; in ddr_reg_save()255 (uint32_t *)(DDR_PCTL_BASE + DDR_PCTL_TOGCNT1U), 35); in ddr_reg_save()257 pctl_tim->SCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_SCFG); in ddr_reg_save()258 pctl_tim->CMDTSTATEN = mmio_read_32(DDR_PCTL_BASE + in ddr_reg_save()260 pctl_tim->MCFG1 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_MCFG1); in ddr_reg_save()261 pctl_tim->MCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_MCFG); in ddr_reg_save()262 pctl_tim->PPCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_PPCFG); in ddr_reg_save()263 pctl_tim->pctl_timing.ddrfreq = mmio_read_32(DDR_PCTL_BASE + in ddr_reg_save()265 pctl_tim->DFITCTRLDELAY = mmio_read_32(DDR_PCTL_BASE + in ddr_reg_save()267 pctl_tim->DFIODTCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFIODTCFG); in ddr_reg_save()[all …]
47 #define DDR_PCTL_BASE 0xff610000 macro
35 MAP_REGION_FLAT(DDR_PCTL_BASE, DDR_PCTL_SIZE,