1 /** @file
2 *
3 *  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
4 *  Copyright (c) 2015, Linaro Limited. All rights reserved.
5 *
6 *  This program and the accompanying materials
7 *  are licensed and made available under the terms and conditions of the BSD License
8 *  which accompanies this distribution.  The full text of the license may be found at
9 *  http://opensource.org/licenses/bsd-license.php
10 *
11 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 *
14 **/
15 
16 
17 #ifndef _SERDES_LIB_H_
18 #define _SERDES_LIB_H_
19 
20 
21 typedef enum {
22   EmHilink0Pcie1X8 = 0,
23   EmHilink0Pcie1X4Pcie2X4 = 1,
24 } HILINK0_MODE_TYPE;
25 
26 typedef enum {
27   EmHilink1Pcie0X8 = 0,
28   EmHilink1HccsX8 = 1,
29 } HILINK1_MODE_TYPE;
30 
31 typedef enum {
32   EmHilink2Pcie2X8 = 0,
33   EmHilink2Sas0X8 = 1,
34 } HILINK2_MODE_TYPE;
35 
36 typedef enum {
37   EmHilink3GeX4 = 0,
38   EmHilink3GeX2XgeX2 = 1, //lane0,lane1-ge,lane2,lane3 xge
39 } HILINK3_MODE_TYPE;
40 
41 
42 typedef enum {
43   EmHilink4GeX4 = 0,
44   EmHilink4XgeX4 = 1,
45 } HILINK4_MODE_TYPE;
46 
47 typedef enum {
48   EmHilink5Sas1X4 = 0,
49   EmHilink5Pcie3X4 = 1,
50 } HILINK5_MODE_TYPE;
51 
52 
53 typedef struct {
54   HILINK0_MODE_TYPE Hilink0Mode;
55   HILINK1_MODE_TYPE Hilink1Mode;
56   HILINK2_MODE_TYPE Hilink2Mode;
57   HILINK3_MODE_TYPE Hilink3Mode;
58   HILINK4_MODE_TYPE Hilink4Mode;
59   HILINK5_MODE_TYPE Hilink5Mode;
60 } SERDES_PARAM;
61 
62 
63 #define SERDES_INVALID_MACRO_ID  0xFFFFFFFF
64 #define SERDES_INVALID_LANE_NUM  0xFFFFFFFF
65 
66 typedef struct {
67     UINT32 MacroId;
68     UINT32 DsNum;
69 } SERDES_POLARITY_INVERT;
70 
71 
72 EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId);
73 extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[];
74 extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[];
75 UINT32 GetEthType(UINT8 EthChannel);
76 
77 EFI_STATUS
78 EfiSerdesInitWrap (VOID);
79 
80 void serdes_state_show(UINT32 macro1);
81 //uniBIOS__l00228991_start DTS2015042210118 2015-4-22 20:06:34
82 
83 void SRE_SerdesEnableCTLEDFE(UINT32 macro, UINT32 lane, UINT32 ulDsCfg);
84 //uniBIOS__l00228991_end DTS2015042210118 2015-4-22 20:06:34
85 
86 //uniBIOS_l00306713_000_start 2015-3-19 17:37:06
87 
88 //EYE test
89 UINT32 serdes_eye_test(UINT32 uwMacroId, UINT32 uwDsNum, UINT32 eyemode, UINT32 scanwindowvalue, UINT32 uwRateData);
90 
91 UINT32 Serdes_ReadBert(UINT32   ulMacroId , UINT32   ulDsNum);
92 
93 //PRBS test
94 int serdes_prbs_test(UINT8   ulMacroId , UINT8   ulDsNum,UINT8 PrbsType);
95 
96 int serdes_prbs_test_cancle(UINT8  ulMacroId,UINT8 ulDsNum);
97 
98 //CTLE/DFE
99 void serdes_ctle_adaptation_close(UINT32 macro,UINT32 lane);
100 
101 void serdes_ctle_adaptation_open(UINT32 macro,UINT32 lane);
102 
103 void serdes_dfe_adaptation_close(UINT32 macro,UINT32 lane);
104 
105 void serdes_dfe_adaptation_open(UINT32 macro,UINT32 lane);
106 
107 void serdes_ctle_dfe_reset(UINT32 macro,UINT32 lane);
108 //uniBIOS_l00306713_000_end   2015-3-19 17:37:06
109 
110 
111 //uniBIOS_l00306713_000_start 2015-7-15 9:13:55
112 
113 int serdes_tx_to_rx_serial_loopback(UINT8 macro,UINT8 lane,UINT8 val);
114 
115 int serdes_tx_to_rx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val);
116 
117 int serdes_rx_to_tx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val);
118 //uniBIOS_l00306713_000_end   2015-7-15 9:13:55
119 
120 #endif
121