1 /*
2 * Copyright (C) 2016 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include <errno.h>
18 #include <stdint.h>
19 #include <string.h>
20
21 #include <gpio.h>
22 #include <i2c.h>
23 #include <seos.h>
24 #include <util.h>
25 #include <gpio.h>
26 #include <atomicBitset.h>
27 #include <atomic.h>
28 #include <platform.h>
29 #include <timer.h>
30
31 #include <plat/cmsis.h>
32 #include <plat/dma.h>
33 #include <plat/gpio.h>
34 #include <plat/i2c.h>
35 #include <plat/pwr.h>
36 #include <plat/plat.h>
37
38 #include <cpu/barrier.h>
39
40 #define I2C_VERBOSE_DEBUG 0
41 #define I2C_MAX_QUEUE_DEPTH 5
42
43 #if I2C_VERBOSE_DEBUG
44 #define i2c_log_debug(x) osLog(LOG_DEBUG, x "\n")
45 #else
46 #define i2c_log_debug(x) do {} while(0)
47 #endif
48
49 #define I2C_CR1_PE (1 << 0)
50 #define I2C_CR1_SMBUS (1 << 1)
51 #define I2C_CR1_SMBTYPE (1 << 3)
52 #define I2C_CR1_ENARP (1 << 4)
53 #define I2C_CR1_ENPEC (1 << 5)
54 #define I2C_CR1_ENGC (1 << 6)
55 #define I2C_CR1_NOSTRETCH (1 << 7)
56 #define I2C_CR1_START (1 << 8)
57 #define I2C_CR1_STOP (1 << 9)
58 #define I2C_CR1_ACK (1 << 10)
59 #define I2C_CR1_POS (1 << 11)
60 #define I2C_CR1_PEC (1 << 12)
61 #define I2C_CR1_ALERT (1 << 13)
62 #define I2C_CR1_SWRST (1 << 15)
63
64 #define I2C_CR2_FREQ(x) ((x) & I2C_CR2_FREQ_MASK)
65 #define I2C_CR2_FREQ_MASK 0x3F
66 #define I2C_CR2_ITERREN (1 << 8)
67 #define I2C_CR2_ITEVTEN (1 << 9)
68 #define I2C_CR2_ITBUFEN (1 << 10)
69 #define I2C_CR2_DMAEN (1 << 11)
70 #define I2C_CR2_LAST (1 << 12)
71
72 #define I2C_OAR1_ADD7(x) (((x) & I2C_OAR1_ADD7_MASK) << 1)
73 #define I2C_OAR1_ADD7_MASK 0x7F
74 #define I2C_OAR1_ADD10(x) ((x) & I2C_OAR1_ADD10_MASK)
75 #define I2C_OAR1_ADD10_MASK 0x3FF
76 #define I2C_OAR1_ADDMODE (1 << 15)
77
78 #define I2C_SR1_SB (1 << 0)
79 #define I2C_SR1_ADDR (1 << 1)
80 #define I2C_SR1_BTF (1 << 2)
81 #define I2C_SR1_ADD10 (1 << 3)
82 #define I2C_SR1_STOPF (1 << 4)
83 #define I2C_SR1_RXNE (1 << 6)
84 #define I2C_SR1_TXE (1 << 7)
85 #define I2C_SR1_BERR (1 << 8)
86 #define I2C_SR1_ARLO (1 << 9)
87 #define I2C_SR1_AF (1 << 10)
88 #define I2C_SR1_OVR (1 << 11)
89 #define I2C_SR1_PECERR (1 << 12)
90 #define I2C_SR1_TIMEOUT (1 << 14)
91 #define I2C_SR1_SMBALERT (1 << 15)
92
93 #define I2C_SR2_MSL (1 << 0)
94 #define I2C_SR2_BUSY (1 << 1)
95 #define I2C_SR2_TRA (1 << 2)
96 #define I2C_SR2_GENCALL (1 << 4)
97 #define I2C_SR2_SMBDEFAULT (1 << 5)
98 #define I2C_SR2_SMBHOST (1 << 6)
99 #define I2C_SR2_DUALF (1 << 7)
100
101 #define I2C_CCR(x) ((x) & I2C_CCR_MASK)
102 #define I2C_CCR_MASK 0xFFF
103 #define I2C_CCR_DUTY_16_9 (1 << 14)
104 #define I2C_CCR_FM (1 << 15)
105
106 #define I2C_TRISE(x) ((x) & I2C_TRISE_MASK)
107 #define I2C_TRISE_MASK 0x3F
108
109 struct StmI2c {
110 volatile uint32_t CR1;
111 volatile uint32_t CR2;
112 volatile uint32_t OAR1;
113 volatile uint32_t OAR2;
114 volatile uint32_t DR;
115 volatile uint32_t SR1;
116 volatile uint32_t SR2;
117 volatile uint32_t CCR;
118 volatile uint32_t TRISE;
119 volatile uint32_t FLTR;
120 };
121
122 enum StmI2cSpiMasterState
123 {
124 STM_I2C_MASTER_IDLE,
125 STM_I2C_MASTER_START,
126 STM_I2C_MASTER_TX_ADDR,
127 STM_I2C_MASTER_TX_DATA,
128 STM_I2C_MASTER_RX_ADDR,
129 STM_I2C_MASTER_RX_DATA,
130 };
131
132 struct I2cStmState {
133 struct {
134 union {
135 uint8_t *buf;
136 const uint8_t *cbuf;
137 uint8_t byte;
138 };
139 size_t size;
140 size_t offset;
141 bool preamble;
142
143 I2cCallbackF callback;
144 void *cookie;
145 } rx, tx;
146
147 enum {
148 STM_I2C_DISABLED,
149 STM_I2C_SLAVE,
150 STM_I2C_MASTER,
151 } mode;
152
153 enum {
154 STM_I2C_SLAVE_IDLE,
155 STM_I2C_SLAVE_RX_ARMED,
156 STM_I2C_SLAVE_RX,
157 STM_I2C_SLAVE_TX_ARMED,
158 STM_I2C_SLAVE_TX,
159 } slaveState;
160
161 // StmI2cSpiMasterState
162 uint8_t masterState;
163 uint16_t tid;
164 };
165
166 struct StmI2cCfg {
167 struct StmI2c *regs;
168
169 uint32_t clock;
170
171 IRQn_Type irqEv;
172 IRQn_Type irqEr;
173 };
174
175 struct StmI2cDev {
176 const struct StmI2cCfg *cfg;
177 const struct StmI2cBoardCfg *board;
178 struct I2cStmState state;
179
180 uint32_t next;
181 uint32_t last;
182
183 struct Gpio *scl;
184 struct Gpio *sda;
185
186 uint8_t addr;
187 };
188
189 static const struct StmI2cCfg mStmI2cCfgs[] = {
190 [0] = {
191 .regs = (struct StmI2c *)I2C1_BASE,
192
193 .clock = PERIPH_APB1_I2C1,
194
195 .irqEv = I2C1_EV_IRQn,
196 .irqEr = I2C1_ER_IRQn,
197 },
198 [1] = {
199 .regs = (struct StmI2c *)I2C2_BASE,
200
201 .clock = PERIPH_APB1_I2C2,
202
203 .irqEv = I2C2_EV_IRQn,
204 .irqEr = I2C2_ER_IRQn,
205 },
206 [2] = {
207 .regs = (struct StmI2c *)I2C3_BASE,
208
209 .clock = PERIPH_APB1_I2C3,
210
211 .irqEv = I2C3_EV_IRQn,
212 .irqEr = I2C3_ER_IRQn,
213 },
214 };
215
216 static struct StmI2cDev mStmI2cDevs[ARRAY_SIZE(mStmI2cCfgs)];
217
218 struct StmI2cXfer
219 {
220 uint32_t id;
221 const void *txBuf;
222 size_t txSize;
223 void *rxBuf;
224 size_t rxSize;
225 I2cCallbackF callback;
226 void *cookie;
227 uint8_t busId; /* for us these are both fine in a uint 8 */
228 uint8_t addr;
229 uint16_t tid;
230 };
231
232 ATOMIC_BITSET_DECL(mXfersValid, I2C_MAX_QUEUE_DEPTH, static);
233 static struct StmI2cXfer mXfers[I2C_MAX_QUEUE_DEPTH] = { };
234
stmI2cGetXfer(void)235 static inline struct StmI2cXfer *stmI2cGetXfer(void)
236 {
237 int32_t idx = atomicBitsetFindClearAndSet(mXfersValid);
238
239 if (idx < 0)
240 return NULL;
241 else
242 return mXfers + idx;
243 }
244
stmI2cPutXfer(struct StmI2cXfer * xfer)245 static inline void stmI2cPutXfer(struct StmI2cXfer *xfer)
246 {
247 if (xfer)
248 atomicBitsetClearBit(mXfersValid, xfer - mXfers);
249 }
250
stmI2cAckEnable(struct StmI2cDev * pdev)251 static inline void stmI2cAckEnable(struct StmI2cDev *pdev)
252 {
253 pdev->cfg->regs->CR1 |= I2C_CR1_ACK;
254 }
255
stmI2cAckDisable(struct StmI2cDev * pdev)256 static inline void stmI2cAckDisable(struct StmI2cDev *pdev)
257 {
258 pdev->cfg->regs->CR1 &= ~I2C_CR1_ACK;
259 }
260
stmI2cDmaEnable(struct StmI2cDev * pdev)261 static inline void stmI2cDmaEnable(struct StmI2cDev *pdev)
262 {
263 pdev->cfg->regs->CR2 |= I2C_CR2_DMAEN;
264 }
265
stmI2cDmaDisable(struct StmI2cDev * pdev)266 static inline void stmI2cDmaDisable(struct StmI2cDev *pdev)
267 {
268 pdev->cfg->regs->CR2 &= ~I2C_CR2_DMAEN;
269 }
270
stmI2cStopEnable(struct StmI2cDev * pdev)271 static inline void stmI2cStopEnable(struct StmI2cDev *pdev)
272 {
273 struct StmI2c *regs = pdev->cfg->regs;
274
275 while (regs->CR1 & (I2C_CR1_STOP | I2C_CR1_START))
276 ;
277 regs->CR1 |= I2C_CR1_STOP;
278 }
279
stmI2cStartEnable(struct StmI2cDev * pdev)280 static inline void stmI2cStartEnable(struct StmI2cDev *pdev)
281 {
282 struct StmI2c *regs = pdev->cfg->regs;
283
284 while (regs->CR1 & (I2C_CR1_STOP | I2C_CR1_START))
285 ;
286 regs->CR1 |= I2C_CR1_START;
287 }
288
stmI2cIrqEnable(struct StmI2cDev * pdev,uint32_t mask)289 static inline void stmI2cIrqEnable(struct StmI2cDev *pdev,
290 uint32_t mask)
291 {
292 pdev->cfg->regs->CR2 |= mask;
293 }
294
stmI2cIrqDisable(struct StmI2cDev * pdev,uint32_t mask)295 static inline void stmI2cIrqDisable(struct StmI2cDev *pdev,
296 uint32_t mask)
297 {
298 pdev->cfg->regs->CR2 &= ~mask;
299 }
300
stmI2cEnable(struct StmI2cDev * pdev)301 static inline void stmI2cEnable(struct StmI2cDev *pdev)
302 {
303 pdev->cfg->regs->CR1 |= I2C_CR1_PE;
304 }
305
stmI2cDisable(struct StmI2cDev * pdev)306 static inline void stmI2cDisable(struct StmI2cDev *pdev)
307 {
308 pdev->cfg->regs->CR1 &= ~I2C_CR1_PE;
309 }
310
stmI2cSpeedSet(struct StmI2cDev * pdev,const uint32_t speed)311 static inline void stmI2cSpeedSet(struct StmI2cDev *pdev,
312 const uint32_t speed)
313 {
314 struct StmI2c *regs = pdev->cfg->regs;
315 int ccr, ccr_1, ccr_2;
316 int apb1_clk;
317
318 apb1_clk = pwrGetBusSpeed(PERIPH_BUS_APB1);
319
320 regs->CR2 = (regs->CR2 & ~I2C_CR2_FREQ_MASK) |
321 I2C_CR2_FREQ(apb1_clk / 1000000);
322
323 if (speed <= 100000) {
324 ccr = apb1_clk / (speed * 2);
325 if (ccr < 4)
326 ccr = 4;
327 regs->CCR = I2C_CCR(ccr);
328
329 regs->TRISE = I2C_TRISE((apb1_clk / 1000000) + 1);
330 } else if (speed <= 400000) {
331 ccr_1 = apb1_clk / (speed * 3);
332 if (ccr_1 == 0 || apb1_clk / (ccr_1 * 3) > speed)
333 ccr_1 ++;
334 ccr_2 = apb1_clk / (speed * 25);
335 if (ccr_2 == 0 || apb1_clk / (ccr_2 * 25) > speed)
336 ccr_2 ++;
337
338 if ((apb1_clk / (ccr_1 * 3)) > (apb1_clk / (ccr_2 * 25)))
339 regs->CCR = I2C_CCR_FM | I2C_CCR(ccr_1);
340 else
341 regs->CCR = I2C_CCR_FM | I2C_CCR_DUTY_16_9 | I2C_CCR(ccr_2);
342
343 regs->TRISE = I2C_TRISE(((3*apb1_clk)/10000000) + 1);
344 }
345 }
346
stmI2cSlaveIdle(struct StmI2cDev * pdev)347 static inline void stmI2cSlaveIdle(struct StmI2cDev *pdev)
348 {
349 struct I2cStmState *state = &pdev->state;
350
351 state->slaveState = STM_I2C_SLAVE_RX_ARMED;
352 stmI2cAckEnable(pdev);
353 stmI2cIrqDisable(pdev, I2C_CR2_ITBUFEN | I2C_CR2_ITERREN);
354 }
355
stmI2cInvokeRxCallback(struct I2cStmState * state,size_t tx,size_t rx,int err)356 static inline void stmI2cInvokeRxCallback(struct I2cStmState *state, size_t tx, size_t rx, int err)
357 {
358 uint16_t oldTid = osSetCurrentTid(state->tid);
359 state->rx.callback(state->rx.cookie, tx, rx, err);
360 osSetCurrentTid(oldTid);
361 }
362
stmI2cInvokeTxCallback(struct I2cStmState * state,size_t tx,size_t rx,int err)363 static inline void stmI2cInvokeTxCallback(struct I2cStmState *state, size_t tx, size_t rx, int err)
364 {
365 uint16_t oldTid = osSetCurrentTid(state->tid);
366 state->tx.callback(state->tx.cookie, tx, rx, err);
367 osSetCurrentTid(oldTid);
368 }
369
stmI2cSlaveRxDone(struct StmI2cDev * pdev)370 static inline void stmI2cSlaveRxDone(struct StmI2cDev *pdev)
371 {
372 struct I2cStmState *state = &pdev->state;
373 size_t rxOffst = state->rx.offset;
374
375 state->rx.offset = 0;
376 stmI2cInvokeRxCallback(state, 0, rxOffst, 0);
377 }
378
stmI2cSlaveTxDone(struct StmI2cDev * pdev)379 static inline void stmI2cSlaveTxDone(struct StmI2cDev *pdev)
380 {
381 struct I2cStmState *state = &pdev->state;
382 size_t txOffst = state->tx.offset;
383
384 stmI2cSlaveIdle(pdev);
385 stmI2cInvokeTxCallback(state, txOffst, 0, 0);
386 }
387
stmI2cSlaveTxNextByte(struct StmI2cDev * pdev)388 static void stmI2cSlaveTxNextByte(struct StmI2cDev *pdev)
389 {
390 struct I2cStmState *state = &pdev->state;
391 struct StmI2c *regs = pdev->cfg->regs;
392
393 if (state->tx.preamble) {
394 regs->DR = state->tx.byte;
395 state->tx.offset++;
396 } else if (state->tx.offset < state->tx.size) {
397 regs->DR = state->tx.cbuf[state->tx.offset];
398 state->tx.offset++;
399 } else {
400 state->slaveState = STM_I2C_SLAVE_TX_ARMED;
401 stmI2cIrqDisable(pdev, I2C_CR2_ITBUFEN);
402 stmI2cInvokeTxCallback(state, state->tx.offset, 0, 0);
403 }
404 }
405
stmI2cSlaveAddrMatched(struct StmI2cDev * pdev)406 static void stmI2cSlaveAddrMatched(struct StmI2cDev *pdev)
407 {
408 struct I2cStmState *state = &pdev->state;
409 struct StmI2c *regs = pdev->cfg->regs;
410
411 i2c_log_debug("addr");
412
413 if (state->slaveState == STM_I2C_SLAVE_RX_ARMED) {
414 state->slaveState = STM_I2C_SLAVE_RX;
415 stmI2cIrqEnable(pdev, I2C_CR2_ITBUFEN | I2C_CR2_ITERREN);
416 } else if (state->slaveState == STM_I2C_SLAVE_TX) {
417 stmI2cIrqEnable(pdev, I2C_CR2_ITBUFEN | I2C_CR2_ITERREN);
418 }
419 /* clear ADDR by doing a dummy reads from SR1 (already read) then SR2 */
420 (void)regs->SR2;
421 }
422
stmI2cSlaveStopRxed(struct StmI2cDev * pdev)423 static void stmI2cSlaveStopRxed(struct StmI2cDev *pdev)
424 {
425 struct StmI2c *regs = pdev->cfg->regs;
426
427 i2c_log_debug("stopf");
428
429 (void)regs->SR1;
430 stmI2cEnable(pdev);
431 /* clear STOPF by doing a dummy read from SR1 and strobing the PE bit */
432
433 stmI2cSlaveIdle(pdev);
434 stmI2cSlaveRxDone(pdev);
435 }
436
stmI2cSlaveRxBufNotEmpty(struct StmI2cDev * pdev)437 static inline void stmI2cSlaveRxBufNotEmpty(struct StmI2cDev *pdev)
438 {
439 struct I2cStmState *state = &pdev->state;
440 struct StmI2c *regs = pdev->cfg->regs;
441 uint8_t data = regs->DR;
442
443 i2c_log_debug("rxne");
444
445 if (state->rx.offset < state->rx.size) {
446 state->rx.buf[state->rx.offset] = data;
447 state->rx.offset++;
448 } else {
449 stmI2cAckDisable(pdev);
450 /* TODO: error on overflow */
451 }
452 }
453
stmI2cSlaveTxBufEmpty(struct StmI2cDev * pdev)454 static void stmI2cSlaveTxBufEmpty(struct StmI2cDev *pdev)
455 {
456 struct I2cStmState *state = &pdev->state;
457
458 i2c_log_debug("txe");
459
460 if (state->slaveState == STM_I2C_SLAVE_RX) {
461 state->slaveState = STM_I2C_SLAVE_TX_ARMED;
462 stmI2cIrqDisable(pdev, I2C_CR2_ITBUFEN);
463 stmI2cAckDisable(pdev);
464 stmI2cSlaveRxDone(pdev);
465 /* stmI2cTxNextByte() will happen when the task provides a
466 TX buffer; the I2C controller will stretch the clock until then */
467 } else {
468 stmI2cSlaveTxNextByte(pdev);
469 }
470 }
471
stmI2cSlaveNakRxed(struct StmI2cDev * pdev)472 static void stmI2cSlaveNakRxed(struct StmI2cDev *pdev)
473 {
474 struct I2cStmState *state = &pdev->state;
475 struct StmI2c *regs = pdev->cfg->regs;
476
477 i2c_log_debug("af");
478
479 if (state->slaveState == STM_I2C_SLAVE_TX) {
480 state->tx.offset--;
481 /* NACKs seem to be preceded by a spurious TXNE, so adjust the offset to
482 compensate (the corresponding byte written to DR was never actually
483 transmitted) */
484 stmI2cSlaveTxDone(pdev);
485 }
486 regs->SR1 &= ~I2C_SR1_AF;
487 }
488
stmI2cMasterTxRxDone(struct StmI2cDev * pdev,int err)489 static inline void stmI2cMasterTxRxDone(struct StmI2cDev *pdev, int err)
490 {
491 struct I2cStmState *state = &pdev->state;
492 size_t txOffst = state->tx.offset;
493 size_t rxOffst = state->rx.offset;
494 uint32_t id;
495 int i;
496 struct StmI2cXfer *xfer;
497
498 if (pdev->board->sleepDev >= 0)
499 platReleaseDevInSleepMode(pdev->board->sleepDev);
500
501 state->tx.offset = 0;
502 state->rx.offset = 0;
503 stmI2cInvokeTxCallback(state, txOffst, rxOffst, err);
504
505 do {
506 id = atomicAdd32bits(&pdev->next, 1);
507 } while (!id);
508
509 for (i=0; i<I2C_MAX_QUEUE_DEPTH; i++) {
510 xfer = &mXfers[i];
511
512 if (xfer->busId == (pdev - mStmI2cDevs) &&
513 atomicCmpXchg32bits(&xfer->id, id, 0)) {
514 pdev->addr = xfer->addr;
515 state->tx.cbuf = xfer->txBuf;
516 state->tx.offset = 0;
517 state->tx.size = xfer->txSize;
518 state->tx.callback = xfer->callback;
519 state->tx.cookie = xfer->cookie;
520 state->rx.buf = xfer->rxBuf;
521 state->rx.offset = 0;
522 state->rx.size = xfer->rxSize;
523 state->rx.callback = NULL;
524 state->rx.cookie = NULL;
525 state->tid = xfer->tid;
526 atomicWriteByte(&state->masterState, STM_I2C_MASTER_START);
527 if (pdev->board->sleepDev >= 0)
528 platRequestDevInSleepMode(pdev->board->sleepDev, 12);
529 stmI2cPutXfer(xfer);
530 stmI2cStartEnable(pdev);
531 return;
532 }
533 }
534
535 atomicWriteByte(&state->masterState, STM_I2C_MASTER_IDLE);
536 }
537
stmI2cMasterDmaTxDone(void * cookie,uint16_t bytesLeft,int err)538 static void stmI2cMasterDmaTxDone(void *cookie, uint16_t bytesLeft, int err)
539 {
540 struct StmI2cDev *pdev = cookie;
541 struct I2cStmState *state = &pdev->state;
542 struct StmI2c *regs = pdev->cfg->regs;
543
544 state->tx.offset = state->tx.size - bytesLeft;
545 state->tx.size = 0;
546
547 stmI2cDmaDisable(pdev);
548
549 while (!(regs->SR1 & I2C_SR1_BTF))
550 ;
551
552 if (err == 0 && state->rx.size > 0) {
553 atomicWriteByte(&state->masterState, STM_I2C_MASTER_START);
554 stmI2cStartEnable(pdev);
555 } else {
556 stmI2cStopEnable(pdev);
557 stmI2cMasterTxRxDone(pdev, err);
558 }
559 }
560
stmI2cMasterDmaRxDone(void * cookie,uint16_t bytesLeft,int err)561 static void stmI2cMasterDmaRxDone(void *cookie, uint16_t bytesLeft, int err)
562 {
563 struct StmI2cDev *pdev = cookie;
564 struct I2cStmState *state = &pdev->state;
565
566 state->rx.offset = state->rx.size - bytesLeft;
567 state->rx.size = 0;
568
569 stmI2cDmaDisable(pdev);
570 stmI2cStopEnable(pdev);
571 stmI2cMasterTxRxDone(pdev, err);
572 }
573
stmI2cMasterDmaCancel(struct StmI2cDev * pdev)574 static inline void stmI2cMasterDmaCancel(struct StmI2cDev *pdev)
575 {
576 struct I2cStmState *state = &pdev->state;
577
578 dmaStop(I2C_DMA_BUS, pdev->board->dmaRx.stream);
579 state->rx.offset = state->rx.size - dmaBytesLeft(I2C_DMA_BUS,
580 pdev->board->dmaRx.stream);
581 dmaStop(I2C_DMA_BUS, pdev->board->dmaTx.stream);
582 state->tx.offset = state->tx.size - dmaBytesLeft(I2C_DMA_BUS,
583 pdev->board->dmaTx.stream);
584
585 stmI2cDmaDisable(pdev);
586 }
587
stmI2cMasterStartDma(struct StmI2cDev * pdev,const struct StmI2cDmaCfg * dmaCfg,const void * buf,size_t size,DmaCallbackF callback,bool rx,bool last)588 static inline void stmI2cMasterStartDma(struct StmI2cDev *pdev,
589 const struct StmI2cDmaCfg *dmaCfg, const void *buf,
590 size_t size, DmaCallbackF callback, bool rx, bool last)
591 {
592 struct StmI2c *regs = pdev->cfg->regs;
593 struct dmaMode mode;
594
595 memset(&mode, 0, sizeof(mode));
596 mode.priority = DMA_PRIORITY_HIGH;
597 mode.direction = rx ? DMA_DIRECTION_PERIPH_TO_MEM :
598 DMA_DIRECTION_MEM_TO_PERIPH;
599 mode.periphAddr = (uintptr_t)®s->DR;
600 mode.minc = true;
601 mode.channel = dmaCfg->channel;
602
603 dmaStart(I2C_DMA_BUS, dmaCfg->stream, buf, size, &mode, callback, pdev);
604 if (last)
605 stmI2cIrqEnable(pdev, I2C_CR2_LAST);
606 else
607 stmI2cIrqDisable(pdev, I2C_CR2_LAST);
608 stmI2cDmaEnable(pdev);
609 }
610
stmI2cMasterSentStart(struct StmI2cDev * pdev)611 static void stmI2cMasterSentStart(struct StmI2cDev *pdev)
612 {
613 struct I2cStmState *state = &pdev->state;
614 struct StmI2c *regs = pdev->cfg->regs;
615
616 if (atomicReadByte(&state->masterState) == STM_I2C_MASTER_START) {
617 if (state->tx.size > 0) {
618 atomicWriteByte(&state->masterState, STM_I2C_MASTER_TX_ADDR);
619 regs->DR = pdev->addr << 1;
620 } else {
621 atomicWriteByte(&state->masterState, STM_I2C_MASTER_RX_ADDR);
622 stmI2cAckEnable(pdev);
623 regs->DR = (pdev->addr << 1) | 0x01;
624 }
625 }
626 }
627
stmI2cMasterSentAddr(struct StmI2cDev * pdev)628 static void stmI2cMasterSentAddr(struct StmI2cDev *pdev)
629 {
630 struct I2cStmState *state = &pdev->state;
631 struct StmI2c *regs = pdev->cfg->regs;
632 uint8_t masterState = atomicReadByte(&state->masterState);
633
634 if (masterState == STM_I2C_MASTER_TX_ADDR) {
635 stmI2cMasterStartDma(pdev, &pdev->board->dmaTx, state->tx.cbuf,
636 state->tx.size, stmI2cMasterDmaTxDone, false, !!state->rx.size);
637 regs->SR2; // Clear ADDR
638 atomicWriteByte(&state->masterState, STM_I2C_MASTER_TX_DATA);
639 } else if (masterState == STM_I2C_MASTER_RX_ADDR) {
640 if (state->rx.size == 1) // Generate NACK here for 1 byte transfers
641 stmI2cAckDisable(pdev);
642
643 stmI2cMasterStartDma(pdev, &pdev->board->dmaRx, state->rx.buf,
644 state->rx.size, stmI2cMasterDmaRxDone, true,
645 state->rx.size > 1);
646 regs->SR2; // Clear ADDR
647 atomicWriteByte(&state->masterState, STM_I2C_MASTER_RX_DATA);
648 }
649 }
650
stmI2cMasterNakRxed(struct StmI2cDev * pdev)651 static void stmI2cMasterNakRxed(struct StmI2cDev *pdev)
652 {
653 struct I2cStmState *state = &pdev->state;
654 struct StmI2c *regs = pdev->cfg->regs;
655 uint8_t masterState = atomicReadByte(&state->masterState);
656 int err = 0;
657
658 if (masterState == STM_I2C_MASTER_TX_ADDR ||
659 masterState == STM_I2C_MASTER_RX_ADDR) {
660 err = -ENXIO;
661 } else if (masterState == STM_I2C_MASTER_TX_DATA ||
662 masterState == STM_I2C_MASTER_RX_DATA) {
663 stmI2cMasterDmaCancel(pdev);
664 err = -EIO;
665 }
666
667 if (err) {
668 regs->SR1 &= ~I2C_SR1_AF;
669 stmI2cStopEnable(pdev);
670 stmI2cMasterTxRxDone(pdev, err);
671 }
672 }
673
stmI2cMasterBusError(struct StmI2cDev * pdev)674 static void stmI2cMasterBusError(struct StmI2cDev *pdev)
675 {
676 struct StmI2c *regs = pdev->cfg->regs;
677
678 stmI2cMasterDmaCancel(pdev);
679 regs->SR1 &= ~I2C_SR1_BERR;
680 stmI2cMasterTxRxDone(pdev, -EIO);
681 }
682
stmI2cMasterArbitrationLoss(struct StmI2cDev * pdev)683 static void stmI2cMasterArbitrationLoss(struct StmI2cDev *pdev)
684 {
685 struct StmI2c *regs = pdev->cfg->regs;
686
687 stmI2cMasterDmaCancel(pdev);
688 regs->SR1 &= ~I2C_SR1_ARLO;
689 stmI2cMasterTxRxDone(pdev, -EBUSY);
690 }
691
stmI2cMasterUnexpectedError(struct StmI2cDev * pdev)692 static void stmI2cMasterUnexpectedError(struct StmI2cDev *pdev)
693 {
694 struct StmI2c *regs = pdev->cfg->regs;
695
696 osLog(LOG_ERROR, "Unexpected I2C ERR interrupt: SR1 = %04lX, SR2 = %04lX\n",
697 regs->SR1, regs->SR2);
698
699 stmI2cMasterDmaCancel(pdev);
700 regs->SR1 = 0;
701 stmI2cMasterTxRxDone(pdev, -EIO);
702 }
703
stmI2cIsrEvent(struct StmI2cDev * pdev)704 static void stmI2cIsrEvent(struct StmI2cDev *pdev)
705 {
706 struct StmI2c *regs = pdev->cfg->regs;
707 uint16_t sr1 = regs->SR1;
708
709 if (pdev->state.mode == STM_I2C_SLAVE) {
710 if (sr1 & I2C_SR1_ADDR) {
711 stmI2cSlaveAddrMatched(pdev);
712 } else if (sr1 & I2C_SR1_RXNE) {
713 stmI2cSlaveRxBufNotEmpty(pdev);
714 } else if (sr1 & I2C_SR1_TXE) {
715 stmI2cSlaveTxBufEmpty(pdev);
716 } else if (sr1 & I2C_SR1_BTF) {
717 if (regs->SR2 & I2C_SR2_TRA)
718 stmI2cSlaveTxBufEmpty(pdev);
719 else
720 stmI2cSlaveRxBufNotEmpty(pdev);
721 } else if (sr1 & I2C_SR1_STOPF) {
722 stmI2cSlaveStopRxed(pdev);
723 }
724 /* TODO: other flags */
725 } else if (pdev->state.mode == STM_I2C_MASTER) {
726 if (sr1 & I2C_SR1_SB)
727 stmI2cMasterSentStart(pdev);
728 else if (sr1 & I2C_SR1_ADDR)
729 stmI2cMasterSentAddr(pdev);
730 }
731 }
732
stmI2cIsrError(struct StmI2cDev * pdev)733 static void stmI2cIsrError(struct StmI2cDev *pdev)
734 {
735 struct StmI2c *regs = pdev->cfg->regs;
736 uint16_t sr1 = regs->SR1;
737
738 if (pdev->state.mode == STM_I2C_SLAVE) {
739 if (sr1 & I2C_SR1_AF)
740 stmI2cSlaveNakRxed(pdev);
741 /* TODO: other flags */
742 } else if (pdev->state.mode == STM_I2C_MASTER) {
743 if (sr1 & I2C_SR1_AF)
744 stmI2cMasterNakRxed(pdev);
745 else if (sr1 & I2C_SR1_BERR)
746 stmI2cMasterBusError(pdev);
747 else if (sr1 & I2C_SR1_ARLO)
748 stmI2cMasterArbitrationLoss(pdev);
749 else
750 stmI2cMasterUnexpectedError(pdev);
751 }
752 }
753
754 #define DECLARE_IRQ_HANDLERS(_n) \
755 extern void I2C##_n##_EV_IRQHandler(); \
756 extern void I2C##_n##_ER_IRQHandler(); \
757 \
758 extern void I2C##_n##_EV_IRQHandler() \
759 { \
760 stmI2cIsrEvent(&mStmI2cDevs[_n - 1]); \
761 } \
762 \
763 extern void I2C##_n##_ER_IRQHandler() \
764 { \
765 stmI2cIsrError(&mStmI2cDevs[_n - 1]); \
766 }
767
768 DECLARE_IRQ_HANDLERS(1);
769 DECLARE_IRQ_HANDLERS(2);
770 DECLARE_IRQ_HANDLERS(3);
771
stmI2cGpioInit(const struct StmI2cBoardCfg * board,const struct StmI2cGpioCfg * cfg)772 static inline struct Gpio* stmI2cGpioInit(const struct StmI2cBoardCfg *board, const struct StmI2cGpioCfg *cfg)
773 {
774 struct Gpio* gpio = gpioRequest(cfg->gpioNum);
775 gpioConfigAlt(gpio, board->gpioSpeed, board->gpioPull, GPIO_OUT_OPEN_DRAIN,
776 cfg->func);
777
778 return gpio;
779 }
780
i2cMasterReset(uint32_t busId,uint32_t speed)781 static int i2cMasterReset(uint32_t busId, uint32_t speed)
782 {
783 struct Gpio *sda, *scl;
784 int cnt = 0;
785 uint32_t delay;
786
787 if (busId >= ARRAY_SIZE(mStmI2cDevs))
788 return -EINVAL;
789
790 const struct StmI2cBoardCfg *board = boardStmI2cCfg(busId);
791 if (!board)
792 return -EINVAL;
793
794 sda = gpioRequest(board->gpioSda.gpioNum);
795 gpioConfigOutput(sda, board->gpioSpeed, GPIO_PULL_NONE, GPIO_OUT_OPEN_DRAIN, 1);
796 if (gpioGet(sda) == 0) {
797 // 50% duty cycle for the clock
798 delay = 500000000UL/speed;
799
800 scl = gpioRequest(board->gpioScl.gpioNum);
801 gpioConfigOutput(scl, board->gpioSpeed, GPIO_PULL_NONE, GPIO_OUT_OPEN_DRAIN, 1);
802 do {
803 // generate clock pulse
804 gpioSet(scl, 1);
805 timDelay(delay);
806 gpioSet(scl, 0);
807 timDelay(delay);
808 cnt ++;
809 } while (gpioGet(sda) == 0 && cnt < 9);
810
811 // generate STOP condition
812 gpioSet(sda, 0);
813 gpioSet(scl, 1);
814 timDelay(delay);
815 gpioSet(sda, 1);
816 timDelay(delay);
817 gpioRelease(scl);
818 }
819 gpioRelease(sda);
820
821 return cnt;
822 }
823
i2cMasterRequest(uint32_t busId,uint32_t speed)824 int i2cMasterRequest(uint32_t busId, uint32_t speed)
825 {
826 if (busId >= ARRAY_SIZE(mStmI2cDevs))
827 return -EINVAL;
828
829 const struct StmI2cBoardCfg *board = boardStmI2cCfg(busId);
830 if (!board)
831 return -EINVAL;
832
833 struct StmI2cDev *pdev = &mStmI2cDevs[busId];
834 struct I2cStmState *state = &pdev->state;
835 const struct StmI2cCfg *cfg = &mStmI2cCfgs[busId];
836
837 if (state->mode == STM_I2C_DISABLED) {
838 state->mode = STM_I2C_MASTER;
839
840 pdev->cfg = cfg;
841 pdev->board = board;
842 pdev->next = 2;
843 pdev->last = 1;
844 atomicBitsetInit(mXfersValid, I2C_MAX_QUEUE_DEPTH);
845
846 i2cMasterReset(busId, speed);
847
848 pdev->scl = stmI2cGpioInit(board, &board->gpioScl);
849 pdev->sda = stmI2cGpioInit(board, &board->gpioSda);
850
851 pwrUnitClock(PERIPH_BUS_APB1, cfg->clock, true);
852
853 stmI2cDisable(pdev);
854
855 pwrUnitReset(PERIPH_BUS_APB1, cfg->clock, true);
856 pwrUnitReset(PERIPH_BUS_APB1, cfg->clock, false);
857
858 stmI2cIrqEnable(pdev, I2C_CR2_ITEVTEN | I2C_CR2_ITERREN);
859 stmI2cSpeedSet(pdev, speed);
860 atomicWriteByte(&state->masterState, STM_I2C_MASTER_IDLE);
861
862 NVIC_EnableIRQ(cfg->irqEr);
863 NVIC_EnableIRQ(cfg->irqEv);
864
865 stmI2cEnable(pdev);
866 return 0;
867 } else {
868 return -EBUSY;
869 }
870 }
871
i2cMasterRelease(uint32_t busId)872 int i2cMasterRelease(uint32_t busId)
873 {
874 if (busId >= ARRAY_SIZE(mStmI2cDevs))
875 return -EINVAL;
876
877 struct StmI2cDev *pdev = &mStmI2cDevs[busId];
878 struct I2cStmState *state = &pdev->state;
879 const struct StmI2cCfg *cfg = pdev->cfg;
880
881 if (state->mode == STM_I2C_MASTER) {
882 if (atomicReadByte(&state->masterState) == STM_I2C_MASTER_IDLE) {
883 state->mode = STM_I2C_DISABLED;
884 stmI2cIrqEnable(pdev, I2C_CR2_ITERREN | I2C_CR2_ITEVTEN);
885 stmI2cDisable(pdev);
886 pwrUnitClock(PERIPH_BUS_APB1, cfg->clock, false);
887
888 gpioRelease(pdev->scl);
889 gpioRelease(pdev->sda);
890
891 return 0;
892 } else {
893 return -EBUSY;
894 }
895 } else {
896 return -EINVAL;
897 }
898 }
899
900
i2cMasterTxRx(uint32_t busId,uint32_t addr,const void * txBuf,size_t txSize,void * rxBuf,size_t rxSize,I2cCallbackF callback,void * cookie)901 int i2cMasterTxRx(uint32_t busId, uint32_t addr,
902 const void *txBuf, size_t txSize, void *rxBuf, size_t rxSize,
903 I2cCallbackF callback, void *cookie)
904 {
905 uint32_t id;
906
907 if (busId >= ARRAY_SIZE(mStmI2cDevs))
908 return -EINVAL;
909 else if (addr & 0x80)
910 return -ENXIO;
911
912 struct StmI2cDev *pdev = &mStmI2cDevs[busId];
913 struct I2cStmState *state = &pdev->state;
914
915 if (state->mode != STM_I2C_MASTER)
916 return -EINVAL;
917
918 struct StmI2cXfer *xfer = stmI2cGetXfer();
919
920 if (xfer) {
921 xfer->busId = busId;
922 xfer->addr = addr;
923 xfer->txBuf = txBuf;
924 xfer->txSize = txSize;
925 xfer->rxBuf = rxBuf;
926 xfer->rxSize = rxSize;
927 xfer->callback = callback;
928 xfer->cookie = cookie;
929 xfer->tid = osGetCurrentTid();
930
931 do {
932 id = atomicAdd32bits(&pdev->last, 1);
933 } while (!id);
934
935 // after this point the transfer can be picked up by the transfer
936 // complete interrupt
937 atomicWrite32bits(&xfer->id, id);
938
939 // only initiate transfer here if we are in IDLE. Otherwise the transfer
940 // completion interrupt will start the next transfer (not necessarily
941 // this one)
942 if (atomicCmpXchgByte((uint8_t *)&state->masterState,
943 STM_I2C_MASTER_IDLE, STM_I2C_MASTER_START)) {
944 // it is possible for this transfer to already be complete by the
945 // time we get here. if so, transfer->id will have been set to 0.
946 if (atomicCmpXchg32bits(&xfer->id, id, 0)) {
947 pdev->addr = xfer->addr;
948 state->tx.cbuf = xfer->txBuf;
949 state->tx.offset = 0;
950 state->tx.size = xfer->txSize;
951 state->tx.callback = xfer->callback;
952 state->tx.cookie = xfer->cookie;
953 state->rx.buf = xfer->rxBuf;
954 state->rx.offset = 0;
955 state->rx.size = xfer->rxSize;
956 state->rx.callback = NULL;
957 state->rx.cookie = NULL;
958 state->tid = xfer->tid;
959 if (pdev->board->sleepDev >= 0)
960 platRequestDevInSleepMode(pdev->board->sleepDev, 12);
961 stmI2cPutXfer(xfer);
962 stmI2cStartEnable(pdev);
963 }
964 }
965 return 0;
966 } else {
967 return -EBUSY;
968 }
969 }
970
i2cSlaveRequest(uint32_t busId,uint32_t addr)971 int i2cSlaveRequest(uint32_t busId, uint32_t addr)
972 {
973 if (busId >= ARRAY_SIZE(mStmI2cDevs))
974 return -EINVAL;
975
976 const struct StmI2cBoardCfg *board = boardStmI2cCfg(busId);
977 if (!board)
978 return -EINVAL;
979
980 struct StmI2cDev *pdev = &mStmI2cDevs[busId];
981 const struct StmI2cCfg *cfg = &mStmI2cCfgs[busId];
982
983 if (pdev->state.mode == STM_I2C_DISABLED) {
984 pdev->state.mode = STM_I2C_SLAVE;
985
986 pdev->addr = addr;
987 pdev->cfg = cfg;
988 pdev->board = board;
989
990 pdev->scl = stmI2cGpioInit(board, &board->gpioScl);
991 pdev->sda = stmI2cGpioInit(board, &board->gpioSda);
992
993 return 0;
994 } else {
995 return -EBUSY;
996 }
997 }
998
i2cSlaveRelease(uint32_t busId)999 int i2cSlaveRelease(uint32_t busId)
1000 {
1001 if (busId >= ARRAY_SIZE(mStmI2cDevs))
1002 return -EINVAL;
1003
1004 struct StmI2cDev *pdev = &mStmI2cDevs[busId];
1005 const struct StmI2cCfg *cfg = pdev->cfg;
1006
1007 if (pdev->state.mode == STM_I2C_SLAVE) {
1008 pdev->state.mode = STM_I2C_DISABLED;
1009 stmI2cIrqDisable(pdev, I2C_CR2_ITERREN | I2C_CR2_ITEVTEN);
1010 stmI2cAckDisable(pdev);
1011 stmI2cDisable(pdev);
1012 pwrUnitClock(PERIPH_BUS_APB1, cfg->clock, false);
1013
1014 gpioRelease(pdev->scl);
1015 gpioRelease(pdev->sda);
1016
1017 return 0;
1018 } else {
1019 return -EBUSY;
1020 }
1021 }
1022
i2cSlaveEnableRx(uint32_t busId,void * rxBuf,size_t rxSize,I2cCallbackF callback,void * cookie)1023 void i2cSlaveEnableRx(uint32_t busId, void *rxBuf, size_t rxSize,
1024 I2cCallbackF callback, void *cookie)
1025 {
1026 struct StmI2cDev *pdev = &mStmI2cDevs[busId];
1027 const struct StmI2cCfg *cfg = pdev->cfg;
1028 struct I2cStmState *state = &pdev->state;
1029
1030 if (pdev->state.mode == STM_I2C_SLAVE) {
1031 state->rx.buf = rxBuf;
1032 state->rx.offset = 0;
1033 state->rx.size = rxSize;
1034 state->rx.callback = callback;
1035 state->rx.cookie = cookie;
1036 state->slaveState = STM_I2C_SLAVE_RX_ARMED;
1037 state->tid = osGetCurrentTid();
1038
1039 pwrUnitClock(PERIPH_BUS_APB1, cfg->clock, true);
1040 pwrUnitReset(PERIPH_BUS_APB1, cfg->clock, true);
1041 pwrUnitReset(PERIPH_BUS_APB1, cfg->clock, false);
1042
1043 NVIC_EnableIRQ(cfg->irqEr);
1044 NVIC_EnableIRQ(cfg->irqEv);
1045
1046 stmI2cEnable(pdev);
1047 cfg->regs->OAR1 = I2C_OAR1_ADD7(pdev->addr);
1048 stmI2cIrqEnable(pdev, I2C_CR2_ITERREN | I2C_CR2_ITEVTEN);
1049 stmI2cAckEnable(pdev);
1050 }
1051 }
1052
i2cSlaveTx(uint32_t busId,const void * txBuf,uint8_t byte,size_t txSize,I2cCallbackF callback,void * cookie)1053 static int i2cSlaveTx(uint32_t busId, const void *txBuf, uint8_t byte,
1054 size_t txSize, I2cCallbackF callback, void *cookie)
1055 {
1056 struct StmI2cDev *pdev = &mStmI2cDevs[busId];
1057 struct I2cStmState *state = &pdev->state;
1058
1059 if (pdev->state.mode == STM_I2C_SLAVE) {
1060 if (state->slaveState == STM_I2C_SLAVE_RX)
1061 return -EBUSY;
1062
1063 if (txBuf) {
1064 state->tx.cbuf = txBuf;
1065 state->tx.preamble = false;
1066 } else {
1067 state->tx.byte = byte;
1068 state->tx.preamble = true;
1069 }
1070 state->tx.offset = 0;
1071 state->tx.size = txSize;
1072 state->tx.callback = callback;
1073 state->tx.cookie = cookie;
1074
1075 if (state->slaveState == STM_I2C_SLAVE_TX_ARMED) {
1076 state->slaveState = STM_I2C_SLAVE_TX;
1077 stmI2cSlaveTxNextByte(pdev);
1078 stmI2cIrqEnable(pdev, I2C_CR2_ITBUFEN);
1079 } else {
1080 state->slaveState = STM_I2C_SLAVE_TX;
1081 }
1082
1083 return 0;
1084 } else {
1085 return -EBUSY;
1086 }
1087 }
1088
i2cSlaveTxPreamble(uint32_t busId,uint8_t byte,I2cCallbackF callback,void * cookie)1089 int i2cSlaveTxPreamble(uint32_t busId, uint8_t byte, I2cCallbackF callback,
1090 void *cookie)
1091 {
1092 return i2cSlaveTx(busId, NULL, byte, 0, callback, cookie);
1093 }
1094
i2cSlaveTxPacket(uint32_t busId,const void * txBuf,size_t txSize,I2cCallbackF callback,void * cookie)1095 int i2cSlaveTxPacket(uint32_t busId, const void *txBuf, size_t txSize,
1096 I2cCallbackF callback, void *cookie)
1097 {
1098 return i2cSlaveTx(busId, txBuf, 0, txSize, callback, cookie);
1099 }
1100