1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PMU_H__ 8 #define __PMU_H__ 9 10 #include <soc.h> 11 12 struct rk3328_sleep_ddr_data { 13 uint32_t pmu_debug_enable; 14 uint32_t debug_iomux_save; 15 uint32_t pmic_sleep_save; 16 uint32_t pmu_wakeup_conf0; 17 uint32_t pmu_pwrmd_com; 18 uint32_t cru_mode_save; 19 uint32_t clk_sel0, clk_sel1, clk_sel18, 20 clk_sel20, clk_sel24, clk_sel38; 21 uint32_t clk_ungt_save[CRU_CLKGATE_NUMS]; 22 uint32_t cru_plls_con_save[MAX_PLL][CRU_PLL_CON_NUMS]; 23 }; 24 25 struct rk3328_sleep_sram_data { 26 uint32_t pmic_sleep_save; 27 uint32_t pmic_sleep_gpio_save[2]; 28 uint32_t ddr_grf_con0; 29 uint32_t dpll_con_save[CRU_PLL_CON_NUMS]; 30 uint32_t pd_sr_idle_save; 31 uint32_t uart2_ier; 32 }; 33 34 /***************************************************************************** 35 * The ways of cores power domain contorlling 36 *****************************************************************************/ 37 enum cores_pm_ctr_mode { 38 core_pwr_pd = 0, 39 core_pwr_wfi = 1, 40 core_pwr_wfi_int = 2 41 }; 42 43 enum pmu_cores_pm_by_wfi { 44 core_pm_en = 0, 45 core_pm_int_wakeup_en, 46 core_pm_dis_int, 47 core_pm_sft_wakeup_en 48 }; 49 50 extern void *pmu_cpuson_entrypoint_start; 51 extern void *pmu_cpuson_entrypoint_end; 52 extern uint64_t cpuson_entry_point[PLATFORM_CORE_COUNT]; 53 extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT]; 54 55 #define CORES_PM_DISABLE 0x0 56 57 /***************************************************************************** 58 * pmu con,reg 59 *****************************************************************************/ 60 #define PMU_WAKEUP_CFG0 0x00 61 #define PMU_PWRDN_CON 0x0c 62 #define PMU_PWRDN_ST 0x10 63 #define PMU_PWRMD_COM 0x18 64 #define PMU_SFT_CON 0x1c 65 #define PMU_INT_CON 0x20 66 #define PMU_INT_ST 0x24 67 #define PMU_POWER_ST 0x44 68 #define PMU_CPUAPM_CON(n) (0x80 + (n) * 4) 69 #define PMU_SYS_REG(n) (0xa0 + (n) * 4) 70 71 #define CHECK_CPU_WFIE_BASE (GRF_BASE + GRF_CPU_STATUS(1)) 72 73 enum pmu_core_pwrst_shift { 74 clst_cpu_wfe = 0, 75 clst_cpu_wfi = 4, 76 }; 77 78 #define clstl_cpu_wfe (clst_cpu_wfe) 79 #define clstb_cpu_wfe (clst_cpu_wfe) 80 81 enum pmu_pd_id { 82 PD_CPU0 = 0, 83 PD_CPU1, 84 PD_CPU2, 85 PD_CPU3, 86 }; 87 88 enum pmu_power_mode_common { 89 pmu_mode_en = 0, 90 sref_enter_en, 91 global_int_disable_cfg, 92 cpu0_pd_en, 93 wait_wakeup_begin_cfg = 4, 94 l2_flush_en, 95 l2_idle_en, 96 ddrio_ret_de_req, 97 ddrio_ret_en = 8, 98 }; 99 100 enum pmu_sft_con { 101 upctl_c_sysreq_cfg = 0, 102 l2flushreq_req, 103 ddr_io_ret_cfg, 104 pmu_sft_ret_cfg, 105 }; 106 107 #define CKECK_WFE_MSK 0x1 108 #define CKECK_WFI_MSK 0x10 109 #define CKECK_WFEI_MSK 0x11 110 111 #define PD_CTR_LOOP 500 112 #define CHK_CPU_LOOP 500 113 #define MAX_WAIT_CONUT 1000 114 115 #define WAKEUP_INT_CLUSTER_EN 0x1 116 #define PMIC_SLEEP_REG 0x34 117 118 #define PLL_IS_NORM_MODE(mode, pll_id) \ 119 ((mode & (PLL_NORM_MODE(pll_id)) & 0xffff) != 0) 120 121 #define CTLR_ENABLE_G1_BIT BIT(1) 122 #define UART_FIFO_EMPTY BIT(6) 123 124 #define UART_IER 0x04 125 #define UART_FCR 0x08 126 #define UART_LSR 0x14 127 128 #define UART_INT_DISABLE 0x00 129 #define UART_FIFO_RESET 0x07 130 131 #endif /* __PMU_H__ */ 132