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Searched refs:PMUCRU_BASE (Results 1 – 7 of 7) sorted by relevance

/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/
Dm0_ctl.c33 mmio_setbits_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, 0x02); in m0_init()
43 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKSEL_CON0, in m0_init()
46 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, WMSK_BIT(5)); in m0_init()
52 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, in m0_start()
59 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, in m0_start()
64 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, in m0_start()
72 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, in m0_stop()
76 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, in m0_stop()
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/
Dsoc.c49 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE); in set_pll_slow_mode()
58 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_NOMAL_MODE); in set_pll_normal_mode()
67 mmio_write_32(PMUCRU_BASE + in set_pll_bypass()
180 mmio_read_32(PMUCRU_BASE + PMUCRU_GATE_CON(i)); in clk_gate_con_save()
192 mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i), REG_SOC_WMSK); in clk_gate_con_disable()
203 mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i), in clk_gate_con_restore()
214 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), in set_plls_nobypass()
232 slp_data.pmucru_rstnhold_con0 = mmio_read_32(PMUCRU_BASE + in set_pmu_rsthold()
234 slp_data.pmucru_rstnhold_con1 = mmio_read_32(PMUCRU_BASE + in set_pmu_rsthold()
256 mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON0, rstnhold_cofig0); in set_pmu_rsthold()
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Dsoc.h277 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), in pmu_sgrf_rst_hld_release()
283 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), in pmu_sgrf_rst_hld()
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/
Ddram.c18 gatedis_con0 = mmio_read_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0); in idle_port()
19 mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, 0x3fffffff); in idle_port()
38 mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, gatedis_con0); in deidle_port()
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/gpio/
Drk3399_gpio.c73 clock_state = (mmio_read_32(PMUCRU_BASE + in gpio_get_clock()
76 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1), in gpio_get_clock()
81 clock_state = (mmio_read_32(PMUCRU_BASE + in gpio_get_clock()
84 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1), in gpio_get_clock()
126 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1), in gpio_put_clock()
131 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1), in gpio_put_clock()
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/include/shared/
Daddressmap_shared.h37 #define PMUCRU_BASE (MMIO_BASE + 0x07750000) macro
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
Dsuspend.c477 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), in dram_all_config()