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Searched refs:Reg (Results 1 – 25 of 74) sorted by relevance

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/device/linaro/bootloader/edk2/ArmPkg/Include/
DAsmMacroIoLib.h31 #define MOV32(Reg, Val) \ argument
32 movw Reg, #(Val) & 0xffff ; \
33 movt Reg, #(Val) >> 16
35 #define ADRL(Reg, Sym) \ argument
36 movw Reg, #:lower16:(Sym) - (. + 16) ; \
37 movt Reg, #:upper16:(Sym) - (. + 12) ; \
38 add Reg, Reg, pc
40 #define LDRL(Reg, Sym) \ argument
41 movw Reg, #:lower16:(Sym) - (. + 16) ; \
42 movt Reg, #:upper16:(Sym) - (. + 12) ; \
[all …]
DAsmMacroIoLib.inc20 adrll $Reg, $Symbol
21 add $Reg, pc, #-8
23 add $Reg, $Reg, #-4
25 add $Reg, $Reg, #0
30 ldrl $Reg, $Symbol
31 add $Reg, pc, #-8
33 add $Reg, $Reg, #-4
35 ldr $Reg, [$Reg, #0]
DAsmMacroIoLibV8.h53 #define MOV32(Reg, Val) \ argument
54 movz Reg, (Val) >> 16, lsl #16 ; \
55 movk Reg, (Val) & 0xffff
57 #define MOV64(Reg, Val) \ argument
58 movz Reg, (Val) >> 48, lsl #48 ; \
59 movk Reg, ((Val) >> 32) & 0xffff, lsl #32 ; \
60 movk Reg, ((Val) >> 16) & 0xffff, lsl #16 ; \
61 movk Reg, (Val) & 0xffff
/device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Phy/MvPhyDxe/
DMvPhyDxe.c70 UINT32 Reg = 0; in MvPhyReset() local
73 Mdio->Read(Mdio, PhyAddr, MII_BMCR, &Reg); in MvPhyReset()
74 Reg |= BMCR_RESET; in MvPhyReset()
75 Mdio->Write(Mdio, PhyAddr, MII_BMCR, Reg); in MvPhyReset()
77 while ((Reg & BMCR_RESET) && timeout--) { in MvPhyReset()
78 Mdio->Read(Mdio, PhyAddr, MII_BMCR, &Reg); in MvPhyReset()
82 if (Reg & BMCR_RESET) { in MvPhyReset()
96 UINT32 Reg; in MvPhyM88e1111sConfig() local
102 Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_CR, &Reg); in MvPhyM88e1111sConfig()
106 Reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); in MvPhyM88e1111sConfig()
[all …]
/device/linaro/bootloader/OpenPlatformPkg/Drivers/Spi/
DMvSpiDxe.c45 UINT32 Spr, BestSpr, Sppr, BestSppr, ClockDivider, Match, Reg, MinBaudDiff; in SpiSetBaudRate() local
83 Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG); in SpiSetBaudRate()
84 Reg &= ~(SPI_SPR_MASK | SPI_SPPR_0_MASK | SPI_SPPR_HI_MASK); in SpiSetBaudRate()
85 Reg |= (BestSpr << SPI_SPR_OFFSET) | in SpiSetBaudRate()
88 MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg); in SpiSetBaudRate()
99 UINT32 Reg, SpiRegBase = PcdGet32 (PcdSpiRegBase); in SpiSetCs() local
101 Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG); in SpiSetCs()
102 Reg &= ~SPI_CS_NUM_MASK; in SpiSetCs()
103 Reg |= (CsId << SPI_CS_NUM_OFFSET); in SpiSetCs()
104 MmioWrite32 (SpiRegBase + SPI_CTRL_REG, Reg); in SpiSetCs()
[all …]
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Library/
DQNCAccessLib.h21 #define MESSAGE_READ_DW(Port, Reg) \ argument
22 …EAD << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFS…
24 #define MESSAGE_WRITE_DW(Port, Reg) \ argument
25 …ITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFS…
27 #define ALT_MESSAGE_READ_DW(Port, Reg) \ argument
28 …EAD << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFS…
30 #define ALT_MESSAGE_WRITE_DW(Port, Reg) \ argument
31 …ITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFS…
33 #define MESSAGE_IO_READ_DW(Port, Reg) \ argument
34 …EAD << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFS…
[all …]
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNC/
DQNCSmmHelpers.c243 switch (BitDesc->Reg.Type) { in ReadBitDesc()
262 Register = (UINT64) IoRead8 (PcdGet16 (PcdPm1blkIoBaseAddress) + BitDesc->Reg.Data.acpi); in ReadBitDesc()
266 Register = (UINT64) IoRead16 (PcdGet16 (PcdPm1blkIoBaseAddress) + BitDesc->Reg.Data.acpi); in ReadBitDesc()
270 Register = (UINT64) IoRead32 (PcdGet16 (PcdPm1blkIoBaseAddress) + BitDesc->Reg.Data.acpi); in ReadBitDesc()
305 …er = (UINT64) IoRead8 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + BitDesc->Reg.Data.gpe); in ReadBitDesc()
309 …r = (UINT64) IoRead16 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + BitDesc->Reg.Data.gpe); in ReadBitDesc()
313 …r = (UINT64) IoRead32 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + BitDesc->Reg.Data.gpe); in ReadBitDesc()
340 CopyMem (&Register, BitDesc->Reg.Data.Mmio, BitDesc->SizeInBytes); in ReadBitDesc()
350 PciBus = BitDesc->Reg.Data.pci.Fields.Bus; in ReadBitDesc()
351 PciDev = BitDesc->Reg.Data.pci.Fields.Dev; in ReadBitDesc()
[all …]
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/
DCpuIA32.c60 OUT EFI_CPUID_REGISTER *Reg OPTIONAL)
67 cmp Reg, 0
69 mov edi, DWORD PTR Reg
71 mov DWORD PTR [edi].RegEax, eax ; Reg->RegEax
72 mov DWORD PTR [edi].RegEbx, ebx ; Reg->RegEbx
73 mov DWORD PTR [edi].RegEcx, ecx ; Reg->RegEcx in EfiReadMsr()
74 mov DWORD PTR [edi].RegEdx, edx ; Reg->RegEdx
184 mov DWORD PTR [edi].RegEax, eax ; Reg->RegEax
185 mov DWORD PTR [edi].RegEbx, ebx ; Reg->RegEbx
186 mov DWORD PTR [edi].RegEcx, ecx ; Reg->RegEcx
[all …]
DCpuIA32.S86 # OUT EFI_CPUID_REGISTER *Reg OPTIONAL)
97 cmpl $0, 0xC(%ebp) # Reg
99 movl 0xC(%ebp), %edi # Reg
101 movl %eax, (%edi) # Reg->RegEax
102 movl %ebx, 4(%edi) # Reg->RegEbx
103 movl %ecx, 8(%edi) # Reg->RegEcx
104 movl %edx, 0xC(%edi) # Reg->RegEdx
224 movl %eax, (%edi) # Reg->RegEax
225 movl %ebx, 4(%edi) # Reg->RegEbx
226 movl %ecx, 8(%edi) # Reg->RegEcx
[all …]
DCpuIA32.asm75 ; OUT EFI_CPUID_REGISTER *Reg OPTIONAL)
86 cmp dword ptr[ebp + 0Ch], 0 ; Reg
88 mov edi,dword ptr [ebp+0Ch] ; Reg
90 mov dword ptr [edi],eax ; Reg->RegEax
91 mov dword ptr [edi+4],ebx ; Reg->RegEbx
92 mov dword ptr [edi+8],ecx ; Reg->RegEcx
93 mov dword ptr [edi+0Ch],edx ; Reg->RegEdx
210 mov dword ptr [edi], eax ; Reg->RegEax
211 mov dword ptr [edi + 4], ebx ; Reg->RegEbx
212 mov dword ptr [edi + 8], ecx ; Reg->RegEcx
[all …]
/device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Cpu/Pentium/CpuIA32Lib/IA32/
DCpuIA32.c48 OUT EFI_CPUID_REGISTER *Reg OPTIONAL) in EfiCpuid()
55 cmp Reg, 0 in EfiCpuid() local
57 mov edi, DWORD PTR Reg in EfiCpuid()
59 mov DWORD PTR [edi].RegEax, eax ; Reg->RegEax in EfiCpuid()
60 mov DWORD PTR [edi].RegEbx, ebx ; Reg->RegEbx in EfiCpuid()
61 mov DWORD PTR [edi].RegEcx, ecx ; Reg->RegEcx in EfiCpuid()
62 mov DWORD PTR [edi].RegEdx, edx ; Reg->RegEdx in EfiCpuid()
172 mov DWORD PTR [edi].RegEax, eax ; Reg->RegEax in EfiCpuidExt()
173 mov DWORD PTR [edi].RegEbx, ebx ; Reg->RegEbx in EfiCpuidExt()
174 mov DWORD PTR [edi].RegEcx, ecx ; Reg->RegEcx in EfiCpuidExt()
[all …]
DCpuIA32.S74 # OUT EFI_CPUID_REGISTER *Reg OPTIONAL)
85 cmpl $0, 0xC(%ebp) # Reg
87 movl 0xC(%ebp), %edi # Reg
89 movl %eax, (%edi) # Reg->RegEax
90 movl %ebx, 4(%edi) # Reg->RegEbx
91 movl %ecx, 8(%edi) # Reg->RegEcx
92 movl %edx, 0xC(%edi) # Reg->RegEdx
212 movl %eax, (%edi) # Reg->RegEax
213 movl %ebx, 4(%edi) # Reg->RegEbx
214 movl %ecx, 8(%edi) # Reg->RegEcx
[all …]
DCpuIA32.asm57 ; OUT EFI_CPUID_REGISTER *Reg OPTIONAL)
68 cmp dword ptr[ebp + 0Ch], 0 ; Reg
70 mov edi,dword ptr [ebp+0Ch] ; Reg
72 mov dword ptr [edi],eax ; Reg->RegEax
73 mov dword ptr [edi+4],ebx ; Reg->RegEbx
74 mov dword ptr [edi+8],ecx ; Reg->RegEcx
75 mov dword ptr [edi+0Ch],edx ; Reg->RegEdx
192 mov dword ptr [edi], eax ; Reg->RegEax
193 mov dword ptr [edi + 4], ebx ; Reg->RegEbx
194 mov dword ptr [edi + 8], ecx ; Reg->RegEcx
[all …]
/device/linaro/bootloader/edk2/OvmfPkg/AcpiTables/
DFacp.aslc40 PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk
41 0, // Power Mgt 1b Event Reg Blk unsupported
42 PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk
43 0, // Power Mgt 1b Ctrl Reg Blk unsupported
44 0, // Power Mgt 2 Ctrl Reg Blk unsupported
45 PM_TMR_BLK, // Port address of Power Mgt Timer Ctrl Reg Blk
46 GPE0_BLK, // Port addr of General Purpose Event 0 Reg Blk
47 0, // General Purpose Event 1 Reg Blk unsupported
50 0, // Power Mgt 2 Ctrl Reg Blk unsupported
53 0, // General Purpose Event 1 Reg Blk unsupported
[all …]
/device/linaro/bootloader/edk2/ArmVirtPkg/HighMemDxe/
DHighMemDxe.c35 CONST UINT32 *Reg; in InitializeHighMemDxe() local
49 (CONST VOID **) &Reg, &AddressCells, in InitializeHighMemDxe()
53 &Node, (CONST VOID **) &Reg, &AddressCells, in InitializeHighMemDxe()
59 CurBase = SwapBytes32 (*Reg++); in InitializeHighMemDxe()
61 CurBase = (CurBase << 32) | SwapBytes32 (*Reg++); in InitializeHighMemDxe()
63 CurSize = SwapBytes32 (*Reg++); in InitializeHighMemDxe()
65 CurSize = (CurSize << 32) | SwapBytes32 (*Reg++); in InitializeHighMemDxe()
/device/linaro/bootloader/edk2/ArmVirtPkg/Library/ArmVirtGicArchLib/
DArmVirtGicArchLib.c38 CONST UINT64 *Reg; in ArmVirtGicArchLibConstructor() local
52 (CONST VOID **)&Reg, &AddressCells, &SizeCells, in ArmVirtGicArchLibConstructor()
57 (CONST VOID **)&Reg, &AddressCells, &SizeCells, in ArmVirtGicArchLibConstructor()
82 DistBase = SwapBytes64 (Reg[0]); in ArmVirtGicArchLibConstructor()
86 RedistBase = SwapBytes64 (Reg[2]); in ArmVirtGicArchLibConstructor()
121 DistBase = SwapBytes64 (Reg[0]); in ArmVirtGicArchLibConstructor()
122 CpuBase = SwapBytes64 (Reg[2]); in ArmVirtGicArchLibConstructor()
/device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/Arm/
DArmV7ArchTimer.c28 IN ARM_ARCH_TIMER_REGS Reg, in ArmArchTimerReadReg() argument
34 switch (Reg) { in ArmArchTimerReadReg()
87 DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg)); in ArmArchTimerReadReg()
100 IN ARM_ARCH_TIMER_REGS Reg, in ArmArchTimerWriteReg() argument
107 switch (Reg) { in ArmArchTimerWriteReg()
161 DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg)); in ArmArchTimerWriteReg()
/device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/AArch64/
DAArch64ArchTimer.c28 IN ARM_ARCH_TIMER_REGS Reg, in ArmArchTimerReadReg() argument
35 switch (Reg) { in ArmArchTimerReadReg()
89 DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg)); in ArmArchTimerReadReg()
100 IN ARM_ARCH_TIMER_REGS Reg, in ArmArchTimerWriteReg() argument
107 switch (Reg) { in ArmArchTimerWriteReg()
161 DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg)); in ArmArchTimerWriteReg()
/device/linaro/bootloader/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/
DFadt2.0.aslc42 ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 1a Event Reg Blk
43 PM1b_EVT_BLK_ADDRESS, // Port address of Power Mgt 1b Event Reg Blk
44 ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 1a Ctrl Reg Blk
45 PM1b_CNT_BLK_ADDRESS, // Port address of Power Mgt 1b Ctrl Reg Blk
46 ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 2 Ctrl Reg Blk
47 ACPI_RUNTIME_UPDATE, // Port address of Power Mgt Timer Ctrl Reg Blk
48 ACPI_RUNTIME_UPDATE, // Port addr of General Purpose Event 0 Reg Blk
49 GPE1_BLK_ADDRESS, // Port addr of General Purpose Event 1 Reg Blk
88 PM1a_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Event Reg Blk
96 PM1b_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Event Reg Blk
[all …]
/device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Cpu/Pentium/CpuIA32Lib/X64/
DCpu.asm64 ; OUT EFI_CPUID_REGISTER *Reg OPTIONAL // rdx
70 mov r8, rdx ; r8 = *Reg
75 mov [r8 + 0], eax ; Reg->RegEax
76 mov [r8 + 4], ebx ; Reg->RegEbx
77 mov [r8 + 8], ecx ; Reg->RegEcx
78 mov [r8 + 12], edx ; Reg->RegEdx
207 mov [r8 + 0 ], eax ; Reg->RegEax
208 mov [r8 + 4 ], ebx ; Reg->RegEbx
209 mov [r8 + 8 ], ecx ; Reg->RegEcx
210 mov [r8 + 12], edx ; Reg->RegEdx
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/
DQNCSmmHelpers.c65 Src1->En[loopvar].Reg.Type != Src2->En[loopvar].Reg.Type || in CompareEnables()
66 Src1->En[loopvar].Reg.Data.raw != Src2->En[loopvar].Reg.Data.raw in CompareEnables()
112 Src1->Sts[loopvar].Reg.Type != Src2->Sts[loopvar].Reg.Type || in CompareStatuses()
113 Src1->Sts[loopvar].Reg.Data.raw != Src2->Sts[loopvar].Reg.Data.raw in CompareStatuses()
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/CpuIA32Lib/X64/
DCpu.asm85 ; OUT EFI_CPUID_REGISTER *Reg OPTIONAL // rdx
91 mov r8, rdx ; r8 = *Reg
96 mov [r8 + 0], eax ; Reg->RegEax
97 mov [r8 + 4], ebx ; Reg->RegEbx
98 mov [r8 + 8], ecx ; Reg->RegEcx
99 mov [r8 + 12], edx ; Reg->RegEdx
228 mov [r8 + 0 ], eax ; Reg->RegEax
229 mov [r8 + 4 ], ebx ; Reg->RegEbx
230 mov [r8 + 8 ], ecx ; Reg->RegEcx
231 mov [r8 + 12], edx ; Reg->RegEdx
/device/linaro/bootloader/edk2/AppPkg/Applications/Python/Python-2.7.2/Lib/distutils/tests/
Dtest_msvc9compiler.py95 from distutils.msvc9compiler import Reg
96 self.assertRaises(KeyError, Reg.get_value, 'xxx', 'xxx')
101 v = Reg.get_value(path, u'dragfullwindows')
106 keys = Reg.read_keys(HKCU, 'xxxx')
109 keys = Reg.read_keys(HKCU, r'Control Panel')
/device/linaro/bootloader/edk2/Omap35xxPkg/Library/OmapDmaLib/
DOmapDmaLib.c150 UINT32 Reg; in DisableDmaChannel() local
158 Reg = MmioRead32 (DMA4_CSR(Channel)); in DisableDmaChannel()
159 if ((Reg & ErrorMask) != 0) { in DisableDmaChannel()
161 DEBUG ((EFI_D_ERROR, "DMA Error (%d) %x\n", Channel, Reg)); in DisableDmaChannel()
164 } while ((Reg & SuccessMask) != SuccessMask); in DisableDmaChannel()
/device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/Dxe/Include/
DEfiRegTableLib.h81 #define PCI_WRITE(Bus, Dev, Fnc, Reg, Width, Data, S3Flag) \ argument
84 (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))), \
96 #define PCI_READ_MODIFY_WRITE(Bus, Dev, Fnc, Reg, Width, OrMask, AndMask, S3Flag) \ argument
99 (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))), \

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