1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __CCI_H__ 8 #define __CCI_H__ 9 10 /* Slave interface offsets from PERIPHBASE */ 11 #define SLAVE_IFACE6_OFFSET 0x7000 12 #define SLAVE_IFACE5_OFFSET 0x6000 13 #define SLAVE_IFACE4_OFFSET 0x5000 14 #define SLAVE_IFACE3_OFFSET 0x4000 15 #define SLAVE_IFACE2_OFFSET 0x3000 16 #define SLAVE_IFACE1_OFFSET 0x2000 17 #define SLAVE_IFACE0_OFFSET 0x1000 18 #define SLAVE_IFACE_OFFSET(index) (SLAVE_IFACE0_OFFSET + \ 19 (0x1000 * (index))) 20 21 /* Slave interface event and count register offsets from PERIPHBASE */ 22 #define EVENT_SELECT7_OFFSET 0x80000 23 #define EVENT_SELECT6_OFFSET 0x70000 24 #define EVENT_SELECT5_OFFSET 0x60000 25 #define EVENT_SELECT4_OFFSET 0x50000 26 #define EVENT_SELECT3_OFFSET 0x40000 27 #define EVENT_SELECT2_OFFSET 0x30000 28 #define EVENT_SELECT1_OFFSET 0x20000 29 #define EVENT_SELECT0_OFFSET 0x10000 30 #define EVENT_OFFSET(index) (EVENT_SELECT0_OFFSET + \ 31 (0x10000 * (index))) 32 33 /* Control and ID register offsets */ 34 #define CTRL_OVERRIDE_REG 0x0 35 #define SECURE_ACCESS_REG 0x8 36 #define STATUS_REG 0xc 37 #define IMPRECISE_ERR_REG 0x10 38 #define PERFMON_CTRL_REG 0x100 39 #define IFACE_MON_CTRL_REG 0x104 40 41 /* Component and peripheral ID registers */ 42 #define PERIPHERAL_ID0 0xFE0 43 #define PERIPHERAL_ID1 0xFE4 44 #define PERIPHERAL_ID2 0xFE8 45 #define PERIPHERAL_ID3 0xFEC 46 #define PERIPHERAL_ID4 0xFD0 47 #define PERIPHERAL_ID5 0xFD4 48 #define PERIPHERAL_ID6 0xFD8 49 #define PERIPHERAL_ID7 0xFDC 50 51 #define COMPONENT_ID0 0xFF0 52 #define COMPONENT_ID1 0xFF4 53 #define COMPONENT_ID2 0xFF8 54 #define COMPONENT_ID3 0xFFC 55 #define COMPONENT_ID4 0x1000 56 #define COMPONENT_ID5 0x1004 57 #define COMPONENT_ID6 0x1008 58 #define COMPONENT_ID7 0x100C 59 60 /* Slave interface register offsets */ 61 #define SNOOP_CTRL_REG 0x0 62 #define SH_OVERRIDE_REG 0x4 63 #define READ_CHNL_QOS_VAL_OVERRIDE_REG 0x100 64 #define WRITE_CHNL_QOS_VAL_OVERRIDE_REG 0x104 65 #define MAX_OT_REG 0x110 66 67 /* Snoop Control register bit definitions */ 68 #define DVM_EN_BIT (1 << 1) 69 #define SNOOP_EN_BIT (1 << 0) 70 #define SUPPORT_SNOOPS (1 << 30) 71 #define SUPPORT_DVM (1 << 31) 72 73 /* Status register bit definitions */ 74 #define CHANGE_PENDING_BIT (1 << 0) 75 76 /* Event and count register offsets */ 77 #define EVENT_SELECT_REG 0x0 78 #define EVENT_COUNT_REG 0x4 79 #define COUNT_CNTRL_REG 0x8 80 #define COUNT_OVERFLOW_REG 0xC 81 82 /* Slave interface monitor registers */ 83 #define INT_MON_REG_SI0 0x90000 84 #define INT_MON_REG_SI1 0x90004 85 #define INT_MON_REG_SI2 0x90008 86 #define INT_MON_REG_SI3 0x9000C 87 #define INT_MON_REG_SI4 0x90010 88 #define INT_MON_REG_SI5 0x90014 89 #define INT_MON_REG_SI6 0x90018 90 91 /* Master interface monitor registers */ 92 #define INT_MON_REG_MI0 0x90100 93 #define INT_MON_REG_MI1 0x90104 94 #define INT_MON_REG_MI2 0x90108 95 #define INT_MON_REG_MI3 0x9010c 96 #define INT_MON_REG_MI4 0x90110 97 #define INT_MON_REG_MI5 0x90114 98 99 #define SLAVE_IF_UNUSED -1 100 101 #ifndef __ASSEMBLY__ 102 103 #include <stdint.h> 104 105 /* Function declarations */ 106 107 /* 108 * The ARM CCI driver needs the following: 109 * 1. Base address of the CCI product 110 * 2. An array of map between AMBA 4 master ids and ACE/ACE lite slave 111 * interfaces. 112 * 3. Size of the array. 113 * 114 * SLAVE_IF_UNUSED should be used in the map to represent no AMBA 4 master exists 115 * for that interface. 116 */ 117 void cci_init(uintptr_t base, const int *map, unsigned int num_cci_masters); 118 119 void cci_enable_snoop_dvm_reqs(unsigned int master_id); 120 void cci_disable_snoop_dvm_reqs(unsigned int master_id); 121 122 #endif /* __ASSEMBLY__ */ 123 #endif /* __CCI_H__ */ 124