Searched refs:SOC_CSS_PCIE_CONTROL_BASE (Results 1 – 2 of 2) sorted by relevance
65 mmio_write_32(SOC_CSS_PCIE_CONTROL_BASE + PCIE_SECURE_REG, in soc_css_init_pcie()
21 #define SOC_CSS_PCIE_CONTROL_BASE 0x7ff20000 macro