1 /** @file
2 *
3 *  Copyright (c) 2016-2017, Linaro Ltd. All rights reserved.
4 *
5 *  This program and the accompanying materials
6 *  are licensed and made available under the terms and conditions of the BSD License
7 *  which accompanies this distribution.  The full text of the license may be found at
8 *  http://opensource.org/licenses/bsd-license.php
9 *
10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 *
13 **/
14 
15 #ifndef __HI3660_H__
16 #define __HI3660_H__
17 
18 #define HKADC_SSI_REG_BASE                      0xE82B8000
19 
20 #define PCTRL_REG_BASE                          0xE8A09000
21 
22 #define PCTRL_CTRL3                             (PCTRL_REG_BASE + 0x010)
23 #define PCTRL_CTRL24                            (PCTRL_REG_BASE + 0x064)
24 
25 #define PCTRL_CTRL3_USB_TXCO_EN                 (1 << 1)
26 #define PCTRL_CTRL24_USB3PHY_3MUX1_SEL          (1 << 25)
27 
28 #define SCTRL_REG_BASE                          0xFFF0A000
29 
30 #define SCTRL_SCFPLLCTRL0                       (SCTRL_REG_BASE + 0x120)
31 #define SCTRL_SCFPLLCTRL0_FPLL0_EN              (1 << 0)
32 
33 #define SCTRL_BAK_DATA0                         (SCTRL_REG_BASE + 0x40C)
34 
35 #define USB3OTG_BC_REG_BASE                     0xFF200000
36 
37 #define USB3OTG_CTRL0                           (USB3OTG_BC_REG_BASE + 0x000)
38 #define USB3OTG_CTRL2                           (USB3OTG_BC_REG_BASE + 0x008)
39 #define USB3OTG_CTRL3                           (USB3OTG_BC_REG_BASE + 0x00C)
40 #define USB3OTG_CTRL4                           (USB3OTG_BC_REG_BASE + 0x010)
41 #define USB3OTG_CTRL6                           (USB3OTG_BC_REG_BASE + 0x018)
42 #define USB3OTG_CTRL7                           (USB3OTG_BC_REG_BASE + 0x01C)
43 #define USB3OTG_PHY_CR_STS                      (USB3OTG_BC_REG_BASE + 0x050)
44 #define USB3OTG_PHY_CR_CTRL                     (USB3OTG_BC_REG_BASE + 0x054)
45 
46 #define USB3OTG_CTRL0_SC_USB3PHY_ABB_GT_EN      (1 << 15)
47 #define USB3OTG_CTRL2_TEST_POWERDOWN_SSP        (1 << 1)
48 #define USB3OTG_CTRL2_TEST_POWERDOWN_HSP        (1 << 0)
49 #define USB3OTG_CTRL3_VBUSVLDEXT                (1 << 6)
50 #define USB3OTG_CTRL3_VBUSVLDEXTSEL             (1 << 5)
51 #define USB3OTG_CTRL7_REF_SSP_EN                (1 << 16)
52 #define USB3OTG_PHY_CR_DATA_OUT(x)              (((x) & 0xFFFF) << 1)
53 #define USB3OTG_PHY_CR_ACK                      (1 << 0)
54 #define USB3OTG_PHY_CR_DATA_IN(x)               (((x) & 0xFFFF) << 4)
55 #define USB3OTG_PHY_CR_WRITE                    (1 << 3)
56 #define USB3OTG_PHY_CR_READ                     (1 << 2)
57 #define USB3OTG_PHY_CR_CAP_DATA                 (1 << 1)
58 #define USB3OTG_PHY_CR_CAP_ADDR                 (1 << 0)
59 
60 #define PMU_REG_BASE                            0xFFF34000
61 #define PMIC_HARDWARE_CTRL0                     (PMU_REG_BASE + (0x0C5 << 2))
62 #define PMIC_OSC32K_ONOFF_CTRL                  (PMU_REG_BASE + (0x0CC << 2))
63 
64 #define PMIC_HARDWARE_CTRL0_WIFI_CLK            (1 << 5)
65 #define PMIC_OSC32K_ONOFF_CTRL_EN_32K           (1 << 1)
66 
67 
68 #define CRG_REG_BASE                            0xFFF35000
69 
70 #define CRG_PEREN2                              (CRG_REG_BASE + 0x020)
71 #define CRG_PERDIS2                             (CRG_REG_BASE + 0x024)
72 #define CRG_PERCLKEN2                           (CRG_REG_BASE + 0x028)
73 #define CRG_PERSTAT2                            (CRG_REG_BASE + 0x02C)
74 #define CRG_PEREN4                              (CRG_REG_BASE + 0x040)
75 #define CRG_PERDIS4                             (CRG_REG_BASE + 0x044)
76 #define CRG_PERCLKEN4                           (CRG_REG_BASE + 0x048)
77 #define CRG_PERSTAT4                            (CRG_REG_BASE + 0x04C)
78 #define CRG_PERRSTEN2                           (CRG_REG_BASE + 0x078)
79 #define CRG_PERRSTDIS2                          (CRG_REG_BASE + 0x07C)
80 #define CRG_PERRSTSTAT2                         (CRG_REG_BASE + 0x080)
81 #define CRG_PERRSTEN3                           (CRG_REG_BASE + 0x084)
82 #define CRG_PERRSTDIS3                          (CRG_REG_BASE + 0x088)
83 #define CRG_PERRSTSTAT3                         (CRG_REG_BASE + 0x08C)
84 #define CRG_PERRSTEN4                           (CRG_REG_BASE + 0x090)
85 #define CRG_PERRSTDIS4                          (CRG_REG_BASE + 0x094)
86 #define CRG_PERRSTSTAT4                         (CRG_REG_BASE + 0x098)
87 #define CRG_ISOEN                               (CRG_REG_BASE + 0x144)
88 #define CRG_ISODIS                              (CRG_REG_BASE + 0x148)
89 #define CRG_ISOSTAT                             (CRG_REG_BASE + 0x14C)
90 
91 #define PERI_UFS_BIT                            (1 << 12)
92 #define PERI_ARST_UFS_BIT                       (1 << 7)
93 
94 #define PEREN2_HKADCSSI                         BIT24
95 
96 #define PEREN4_GT_ACLK_USB3OTG                  (1 << 1)
97 #define PEREN4_GT_CLK_USB3OTG_REF               (1 << 0)
98 
99 #define PERRSTEN2_HKADCSSI                      BIT24
100 
101 #define PERRSTEN4_USB3OTG_MUX                   (1 << 8)
102 #define PERRSTEN4_USB3OTG_AHBIF                 (1 << 7)
103 #define PERRSTEN4_USB3OTG_32K                   (1 << 6)
104 #define PERRSTEN4_USB3OTG                       (1 << 5)
105 #define PERRSTEN4_USB3OTGPHY_POR                (1 << 3)
106 
107 #define PERISOEN_USB_REFCLK_ISO_EN              (1 << 25)
108 
109 #define CRG_CLKDIV16_OFFSET                     0x0E8
110 #define SC_DIV_UFSPHY_CFG_MASK                  (0x3 << 9)
111 #define SC_DIV_UFSPHY_CFG(x)                    (((x) & 0x3) << 9)
112 
113 #define CRG_CLKDIV17_OFFSET                     0x0EC
114 #define SC_DIV_UFS_PERIBUS                      (1 << 14)
115 
116 #define UFS_SYS_REG_BASE                        0xFF3B1000
117 
118 #define UFS_SYS_PSW_POWER_CTRL_OFFSET           0x004
119 #define UFS_SYS_PHY_ISO_EN_OFFSET               0x008
120 #define UFS_SYS_HC_LP_CTRL_OFFSET               0x00C
121 #define UFS_SYS_PHY_CLK_CTRL_OFFSET             0x010
122 #define UFS_SYS_PSW_CLK_CTRL_OFFSET             0x014
123 #define UFS_SYS_CLOCK_GATE_BYPASS_OFFSET        0x018
124 #define UFS_SYS_RESET_CTRL_EN_OFFSET            0x01C
125 #define UFS_SYS_MONITOR_HH_OFFSET               0x03C
126 #define UFS_SYS_UFS_SYSCTRL_OFFSET              0x05C
127 #define UFS_SYS_UFS_DEVICE_RESET_CTRL_OFFSET    0x060
128 #define UFS_SYS_UFS_APB_ADDR_MASK_OFFSET        0x064
129 
130 #define BIT_UFS_PSW_ISO_CTRL                    (1 << 16)
131 #define BIT_UFS_PSW_MTCMOS_EN                   (1 << 0)
132 #define BIT_UFS_REFCLK_ISO_EN                   (1 << 16)
133 #define BIT_UFS_PHY_ISO_CTRL                    (1 << 0)
134 #define BIT_SYSCTRL_LP_ISOL_EN                  (1 << 16)
135 #define BIT_SYSCTRL_PWR_READY                   (1 << 8)
136 #define BIT_SYSCTRL_REF_CLOCK_EN                (1 << 24)
137 #define MASK_SYSCTRL_REF_CLOCK_SEL              (3 << 8)
138 #define MASK_SYSCTRL_CFG_CLOCK_FREQ             (0xFF)
139 #define BIT_SYSCTRL_PSW_CLK_EN                  (1 << 4)
140 #define MASK_UFS_CLK_GATE_BYPASS                (0x3F)
141 #define BIT_SYSCTRL_LP_RESET_N                  (1 << 0)
142 #define BIT_UFS_REFCLK_SRC_SE1                  (1 << 0)
143 #define MASK_UFS_SYSCTRL_BYPASS                 (0x3F << 16)
144 #define MASK_UFS_DEVICE_RESET                   (1 << 16)
145 #define BIT_UFS_DEVICE_RESET                    (1 << 0)
146 
147 #define SCTRL_SCBAKDATA7                        (SCTRL_REG_BASE + 0x428)
148 #define HIKEY_REGION_SIZE(x)                    ((((x) >> 0x8) & 0xF) << 30)
149 
150 #endif /* __HI3660_H__ */
151