Searched refs:ULL (Results 1 – 25 of 54) sorted by relevance
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28 #define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6)29 #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)30 #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)31 #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)34 #define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)46 #define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59)47 #define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54)48 #define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52)49 #define CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)50 #define CORTEX_A57_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)[all …]
19 #define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)20 #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)21 #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)22 #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)34 #define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)35 #define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)36 #define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)37 #define CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32)
19 #define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)20 #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)21 #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)22 #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)34 #define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)35 #define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)36 #define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)37 #define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32)
46 #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59)47 #define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54)48 #define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52)49 #define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)50 #define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)51 #define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38)52 #define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32)53 #define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27)54 #define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25)55 #define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)
32 #define TLK_REQUEST_DONE (0x32000001 | (ULL(1) << 31))33 #define TLK_PREEMPTED (0x32000002 | (ULL(1) << 31))34 #define TLK_ENTRY_DONE (0x32000003 | (ULL(1) << 31))35 #define TLK_VA_TRANSLATE (0x32000004 | (ULL(1) << 31))36 #define TLK_SUSPEND_DONE (0x32000005 | (ULL(1) << 31))37 #define TLK_RESUME_DONE (0x32000006 | (ULL(1) << 31))38 #define TLK_SYSTEM_OFF_DONE (0x32000007 | (ULL(1) << 31))
232 #define VTTBR_RESET_VAL ULL(0x0)233 #define VTTBR_VMID_MASK ULL(0xff)235 #define VTTBR_BADDR_MASK ULL(0xffffffffffff)240 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)332 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)333 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)334 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000)335 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000)336 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)337 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)[all …]
17 #define CLUSTER_CSTATE_MASK ULL(0x7)19 #define CLUSTER_CSTATE_UPDATE_BIT (ULL(1) << 7)20 #define CCPLEX_CSTATE_MASK ULL(0x3)21 #define CCPLEX_CSTATE_SHIFT ULL(8)22 #define CCPLEX_CSTATE_UPDATE_BIT (ULL(1) << 15)23 #define SYSTEM_CSTATE_MASK ULL(0xF)24 #define SYSTEM_CSTATE_SHIFT ULL(16)25 #define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT ULL(22)26 #define SYSTEM_CSTATE_FORCE_UPDATE_BIT (ULL(1) << 22)27 #define SYSTEM_CSTATE_UPDATE_BIT (ULL(1) << 23)[all …]
48 #define MIN_VIRT_ADDR_SPACE_SIZE (ULL(1) << (64 - TCR_TxSZ_MAX))49 #define MAX_VIRT_ADDR_SPACE_SIZE (ULL(1) << (64 - TCR_TxSZ_MIN))73 (((virt_addr_space_size) > (ULL(1) << L0_XLAT_ADDRESS_SHIFT)) \75 : (((virt_addr_space_size) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT)) \
47 #define XN (ULL(1) << 2)49 #define UXN (ULL(1) << 2)50 #define PXN (ULL(1) << 1)51 #define CONT_HINT (ULL(1) << 0)52 #define UPPER_ATTRS(x) (((x) & ULL(0x7)) << 52)60 #define TABLE_ADDR_MASK ULL(0x0000FFFFFFFFF000)102 (((virtual_addr) >> XLAT_ADDR_SHIFT(level)) & ULL(0x1FF))
46 #define MIN_VIRT_ADDR_SPACE_SIZE (ULL(1) << (32 - TTBCR_TxSZ_MAX))47 #define MAX_VIRT_ADDR_SPACE_SIZE (ULL(1) << (32 - TTBCR_TxSZ_MIN))70 (((virt_addr_space_size) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT)) ? 1 : 2)
56 #define UINT64_C(c) c ## ULL61 #define UINTMAX_C(c) c ## ULL
57 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)58 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
18 #define TEGRA_DRAM_BASE ULL(0x80000000)19 #define TEGRA_DRAM_END ULL(0x27FFFFFFF)
81 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x8000)84 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x00200000)
71 #define ARM_TZC_DRAM1_SIZE ULL(0x01000000)87 #define ARM_EL3_TZC_DRAM1_SIZE ULL(0x00200000) /* 2 MB */147 #define ARM_DRAM1_BASE ULL(0x80000000)148 #define ARM_DRAM1_SIZE ULL(0x80000000)152 #define ARM_DRAM2_BASE ULL(0x880000000)
137 #define HNF_SAM_CTRL_TAB0_MASK ULL(0x3f)139 #define HNF_SAM_CTRL_TAB1_MASK ULL(0x3f)143 #define HNF_SAM_CTRL_3SN_ENB_MASK ULL(0x01)
60 #define PERF_INIT_CUM_DATA(t) { 0ULL, PERF_MAXDUR, 0ULL, (t), 0U }
43 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x0)45 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000)
29 #define SRC_REP_C(c) c ## ULL62 #define DST_REP_C(c) c ## ULL
81 # define ULL(_x) (_x) macro84 # define ULL(_x) (_x##ull) macro
39 #define SMC_TYPE_FAST ULL(1)41 #define SMC_TYPE_STD ULL(0)