Searched refs:WRITE_REG32 (Results 1 – 5 of 5) sorted by relevance
/device/linaro/bootloader/OpenPlatformPkg/Drivers/Usb/DwUsbDxe/ |
D | DwUsbDxe.c | 88 WRITE_REG32 (DIEPCTL0, DXEPCTL_USBACTEP | BIT11); in ResetEndpoints() 91 WRITE_REG32 (DOEPCTL0, DXEPCTL_USBACTEP); in ResetEndpoints() 94 WRITE_REG32 (GOTGINT, ~0); in ResetEndpoints() 97 WRITE_REG32 (GINTSTS, ~0); in ResetEndpoints() 98 WRITE_REG32 (DIEPINT0, ~0); in ResetEndpoints() 99 WRITE_REG32 (DOEPINT0, ~0); in ResetEndpoints() 100 WRITE_REG32 (DIEPINT1, ~0); in ResetEndpoints() 101 WRITE_REG32 (DOEPINT1, ~0); in ResetEndpoints() 104 WRITE_REG32 (DIEPMSK, DXEPMSK_TIMEOUTMSK | DXEPMSK_AHBERMSK | DXEPMSK_XFERCOMPLMSK); in ResetEndpoints() 106 WRITE_REG32 (DOEPMSK, DXEPMSK_TIMEOUTMSK | DXEPMSK_AHBERMSK | DXEPMSK_XFERCOMPLMSK); in ResetEndpoints() [all …]
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D | DwUsbDxe.h | 22 #define WRITE_REG32(Offset, Val) MmioWrite32 (DW_USB_BASE + Offset, Val) macro
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/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Isp1761UsbDxe/ |
D | Isp1761UsbDxe.c | 77 WRITE_REG32 (ISP1761_DMA_ENDPOINT_INDEX, ((Endpoint + 2) % ISP1761_NUM_ENDPOINTS)); in SelectEndpoint() 78 WRITE_REG32 (ISP1761_ENDPOINT_INDEX, Endpoint); in SelectEndpoint() 89 WRITE_REG32 (ISP1761_CTRL_FUNCTION, ISP1761_CTRL_FUNCTION_DSEN); in DataStageEnable() 100 WRITE_REG32 (ISP1761_CTRL_FUNCTION, ISP1761_CTRL_FUNCTION_STATUS); in StatusAcknowledge() 189 WRITE_REG32 (ISP1761_DATA_PORT, DwordBuffer[Index]); in WriteEndpointBuffer() 198 WRITE_REG32 (ISP1761_BUFFER_LENGTH, Size); in WriteEndpointBuffer() 201 WRITE_REG32 (ISP1761_DATA_PORT, DwordBuffer[0]); in WriteEndpointBuffer() 207 WRITE_REG32 (ISP1761_DATA_PORT, DwordBuffer[0]); in WriteEndpointBuffer() 297 WRITE_REG32 (ISP1761_ADDRESS, Request->Value | ISP1761_ADDRESS_DEVEN); in HandleSetAddress() 333 WRITE_REG32 (ISP1761_ENDPOINT_MAX_PACKET_SIZE, EPDesc->MaxPacketSize); in HandleSetConfiguration() [all …]
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D | Isp1761UsbDxe.h | 22 #define WRITE_REG32(Offset, Val) MmioWrite32 (ISP1761_USB_BASE + Offset, Val) macro
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/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Drivers/SasV1Dxe/ |
D | SasV1Dxe.c | 36 #define WRITE_REG32(Base, Offset, Val) MmioWrite32 ((Base) + (Offset), (Val)) macro 424 WRITE_REG32(base, DLVRY_Q_0_WR_PTR + queue * 0x14, ++w % QUEUE_SLOTS); in prepare_cmd() 449 WRITE_REG32(base, COMPL_Q_0_RD_PTR + (0x14 * queue), w); in prepare_cmd() 451 WRITE_REG32(base, OQ_INT_SRC, BIT(queue)); in prepare_cmd() 518 WRITE_REG32(base, DLVRY_QUEUE_ENABLE, 0xffffffff); in hisi_sas_v1_init() 519 WRITE_REG32(base, HGC_TRANS_TASK_CNT_LIMIT, 0x11); in hisi_sas_v1_init() 520 WRITE_REG32(base, DEVICE_MSG_WORK_MODE, 0x1); in hisi_sas_v1_init() 521 WRITE_REG32(base, HGC_SAS_TXFAIL_RETRY_CTRL, 0x1ff); in hisi_sas_v1_init() 522 WRITE_REG32(base, HGC_ERR_STAT_EN, 0x401); in hisi_sas_v1_init() 523 WRITE_REG32(base, CFG_1US_TIMER_TRSH, 0x64); in hisi_sas_v1_init() [all …]
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