1 /*
2  * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef __PLAT_PRIVATE_H__
8 #define __PLAT_PRIVATE_H__
9 
10 #ifndef __ASSEMBLY__
11 #include <mmio.h>
12 #include <psci.h>
13 #include <stdint.h>
14 #include <xlat_tables.h>
15 
16 #define __sramdata __attribute__((section(".sram.data")))
17 #define __sramconst __attribute__((section(".sram.rodata")))
18 #define __sramfunc __attribute__((section(".sram.text")))
19 
20 #define __pmusramdata __attribute__((section(".pmusram.data")))
21 #define __pmusramconst __attribute__((section(".pmusram.rodata")))
22 #define __pmusramfunc __attribute__((section(".pmusram.text")))
23 
24 extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end;
25 extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end;
26 extern uint32_t __bl31_sram_stack_start, __bl31_sram_stack_end;
27 extern uint32_t __bl31_sram_text_real_end, __bl31_sram_data_real_end;
28 extern uint32_t __sram_incbin_start, __sram_incbin_end;
29 extern uint32_t __sram_incbin_real_end;
30 
31 
32 /******************************************************************************
33  * The register have write-mask bits, it is mean, if you want to set the bits,
34  * you needs set the write-mask bits at the same time,
35  * The write-mask bits is in high 16-bits.
36  * The fllowing macro definition helps access write-mask bits reg efficient!
37  ******************************************************************************/
38 #define REG_MSK_SHIFT	16
39 
40 #ifndef WMSK_BIT
41 #define WMSK_BIT(nr)		BIT((nr) + REG_MSK_SHIFT)
42 #endif
43 
44 /* set one bit with write mask */
45 #ifndef BIT_WITH_WMSK
46 #define BIT_WITH_WMSK(nr)	(BIT(nr) | WMSK_BIT(nr))
47 #endif
48 
49 #ifndef BITS_SHIFT
50 #define BITS_SHIFT(bits, shift)	(bits << (shift))
51 #endif
52 
53 #ifndef BITS_WITH_WMASK
54 #define BITS_WITH_WMASK(bits, msk, shift)\
55 	(BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT)))
56 #endif
57 
58 /******************************************************************************
59  * Function and variable prototypes
60  *****************************************************************************/
61 void plat_configure_mmu_el3(unsigned long total_base,
62 			    unsigned long total_size,
63 			    unsigned long,
64 			    unsigned long,
65 			    unsigned long,
66 			    unsigned long);
67 
68 void plat_cci_init(void);
69 void plat_cci_enable(void);
70 void plat_cci_disable(void);
71 
72 void plat_delay_timer_init(void);
73 
74 void params_early_setup(void *plat_params_from_bl2);
75 
76 void plat_rockchip_gic_driver_init(void);
77 void plat_rockchip_gic_init(void);
78 void plat_rockchip_gic_cpuif_enable(void);
79 void plat_rockchip_gic_cpuif_disable(void);
80 void plat_rockchip_gic_pcpu_init(void);
81 
82 void plat_rockchip_pmu_init(void);
83 void plat_rockchip_soc_init(void);
84 uintptr_t plat_get_sec_entrypoint(void);
85 
86 void platform_cpu_warmboot(void);
87 
88 struct gpio_info *plat_get_rockchip_gpio_reset(void);
89 struct gpio_info *plat_get_rockchip_gpio_poweroff(void);
90 struct gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count);
91 struct apio_info *plat_get_rockchip_suspend_apio(void);
92 void plat_rockchip_gpio_init(void);
93 void plat_rockchip_save_gpio(void);
94 void plat_rockchip_restore_gpio(void);
95 
96 int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint);
97 int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl,
98 				 plat_local_state_t lvl_state);
99 int rockchip_soc_cores_pwr_dm_off(void);
100 int rockchip_soc_sys_pwr_dm_suspend(void);
101 int rockchip_soc_cores_pwr_dm_suspend(void);
102 int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl,
103 				     plat_local_state_t lvl_state);
104 int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl,
105 				       plat_local_state_t lvl_state);
106 int rockchip_soc_cores_pwr_dm_on_finish(void);
107 int rockchip_soc_sys_pwr_dm_resume(void);
108 
109 int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl,
110 				    plat_local_state_t lvl_state);
111 int rockchip_soc_cores_pwr_dm_resume(void);
112 void __dead2 rockchip_soc_soft_reset(void);
113 void __dead2 rockchip_soc_system_off(void);
114 void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi(
115 				const psci_power_state_t *target_state);
116 void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void);
117 
118 extern const unsigned char rockchip_power_domain_tree_desc[];
119 
120 extern void *pmu_cpuson_entrypoint;
121 extern uint64_t cpuson_entry_point[PLATFORM_CORE_COUNT];
122 extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT];
123 
124 extern const mmap_region_t plat_rk_mmap[];
125 
126 void rockchip_plat_mmu_el3(void);
127 
128 #endif /* __ASSEMBLY__ */
129 
130 /******************************************************************************
131  * cpu up status
132  * The bits of macro value is not more than 12 bits for cmp instruction!
133  ******************************************************************************/
134 #define PMU_CPU_HOTPLUG		0xf00
135 #define PMU_CPU_AUTO_PWRDN	0xf0
136 #define PMU_CLST_RET	0xa5
137 
138 #endif /* __PLAT_PRIVATE_H__ */
139