Home
last modified time | relevance | path

Searched refs:c0 (Results 1 – 25 of 56) sorted by relevance

123

/device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/Arm/
DArmLibSupport.asm22 mrc p15,0,R0,c0,c0,0
26 mrc p15,0,R0,c0,c0,1
44 mcr p15,0,r0,c3,c0,0
65 mrc p15, 0, r0, c1, c0, 2
69 mcr p15, 0, r0, c1, c0, 2
74 mcr p15, 0, r0, c1, c0, 1
78 mrc p15, 0, r0, c1, c0, 1
82 mcr p15,0,r0,c2,c0,0
87 mcr p15, 0, r0, c2, c0, 2
92 mrc p15,0,r0,c2,c0,0
[all …]
DArmV7Support.S71 mrc p15,0,R0,c1,c0,0
73 mcr p15,0,R0,c1,c0,0
80 mrc p15,0,R0,c1,c0,0
82 mcr p15,0,R0,c1,c0,0 @Disable MMU
91 mrc p15, 0, r0, c1, c0, 0 @ Get control register
95 mcr p15, 0, r0, c1, c0, 0 @ Write control register
101 mrc p15,0,R0,c1,c0,0
107 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
109 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
116 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
[all …]
DArmV7Support.asm74 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
76 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
82 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
84 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
93 mrc p15, 0, r0, c1, c0, 0 ; Get control register
97 mcr p15, 0, r0, c1, c0, 0 ; Write control register
103 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
109 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
111 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
118 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
[all …]
DArmLibSupport.S20 mrc p15,0,R0,c0,c0,0
24 mrc p15,0,R0,c0,c0,1
42 mcr p15,0,r0,c3,c0,0
63 mrc p15, 0, r0, c1, c0, 2
67 mcr p15, 0, r0, c1, c0, 2
72 mcr p15, 0, r0, c1, c0, 1
76 mrc p15, 0, r0, c1, c0, 1
80 mcr p15,0,r0,c2,c0,0
85 mcr p15, 0, r0, c2, c0, 2
90 mrc p15,0,r0,c2,c0,0
[all …]
DArmLibSupportV7.asm24 mrc p15,0,R0,c0,c0,5
78 mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
80 mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
88 mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
DArmLibSupportV7.S20 mrc p15,0,R0,c0,c0,5
74 mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
76 mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
84 mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
/device/linaro/bootloader/arm-trusted-firmware/include/lib/aarch32/
Darch.h387 #define SCTLR p15, 0, c1, c0, 0
389 #define MPIDR p15, 0, c0, c0, 5
390 #define MIDR p15, 0, c0, c0, 0
391 #define VBAR p15, 0, c12, c0, 0
392 #define MVBAR p15, 0, c12, c0, 1
394 #define CPACR p15, 0, c1, c0, 2
401 #define CTR p15, 0, c0, c0, 1
402 #define CNTFRQ p15, 0, c14, c0, 0
403 #define ID_PFR1 p15, 0, c0, c1, 1
406 #define TTBCR p15, 0, c2, c0, 2
[all …]
/device/linaro/bootloader/edk2/ArmPkg/Library/ArmMmuLib/Arm/
DArmMmuLibV7Support.asm23 mrc p15,0,R0,c0,c0,5
29 mrc p15, 0, r0, c0, c1, 4 ; Read ID_MMFR0 Register
DArmMmuLibV7Support.S26 mrc p15,0,R0,c0,c0,5
32 mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0 Register
/device/google/contexthub/firmware/lib/libc/
Dmemset.c56 #define VAL c0 in bzero()
60 memset(void *dst0, int c0, size_t length) in bzero()
92 if ((c = (u_char)c0) != 0) { /* Fill the word. */ in bzero()
/device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/Arm/
DRTSMHelper.asm42 mrc p15, 4, r0, c15, c0, 0
61 mrc p15, 0, r1, c0, c0, 0
80 mrc p15, 1, r0, c9, c0, 2 ; Read C9 register of CP15 to get CPU count
DRTSMHelper.S28 mrc p15, 4, r0, c15, c0, 0
45 mrc p15, 0, r1, c0, c0, 0
64 mrc p15, 1, r0, c9, c0, 2 @ Read C9 register of CP15 to get CPU count
/device/linaro/bootloader/arm-trusted-firmware/include/lib/cpus/aarch32/
Dcortex_a53.h52 #define CORTEX_A53_L2ACTLR p15, 1, c15, c0, 0
60 #define CORTEX_A53_L2ECTLR p15, 1, c9, c0, 3
Dcortex_a57.h60 #define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2
71 #define CORTEX_A57_L2ECTLR p15, 1, c9, c0, 3
Dcortex_a72.h42 #define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2
/device/linaro/bootloader/edk2/AppPkg/Applications/Python/Python-2.7.2/Lib/lib2to3/
Dpytree.py783 for c0, r0 in results:
785 if c0 < nodelen and c0 <= self.max:
787 for c1, r1 in generate_matches(alt, nodes[c0:]):
792 yield c0 + c1, r
793 new_results.append((c0 + c1, r))
819 for c0, r0 in generate_matches(alt, nodes):
820 for c1, r1 in self._recursive_matches(nodes[c0:], count+1):
824 yield c0 + c1, r
879 for c0, r0 in p.generate_matches(nodes):
881 yield c0, r0
[all …]
/device/linaro/bootloader/edk2/MdeModulePkg/Universal/RegularExpressionDxe/Oniguruma/enc/
Dutf16_le.c87 UChar c0 = *p; in utf16le_mbc_to_code() local
91 code = ((((c1 - 0xd8) << 2) + ((c0 & 0xc0) >> 6) + 1) << 16) in utf16le_mbc_to_code()
92 + ((((c0 & 0x3f) << 2) + (p[3] - 0xdc)) << 8) in utf16le_mbc_to_code()
/device/google/contexthub/util/nanoapp_sign/
Dtest_exponent4 21:34:1c:0c:d2:8a:b8:77:ff:18:d7:94:8c:c0:b7:
12 52:f9:e7:43:29:b3:80:78:e3:45:b7:3f:ae:03:c0:
/device/linaro/bootloader/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/
DArmCortexA9Helper.S22 mrc p15, 4, r0, c15, c0, 0
DArmCortexA9Helper.asm26 mrc p15, 4, r0, c15, c0, 0
/device/linaro/bootloader/edk2/ArmPkg/Library/DebugAgentSymbolsBaseLib/Arm/
DDebugAgentException.asm182 mrc p15, 0, R1, c6, c0, 2 ; Read IFAR
185 mrc p15, 0, R1, c5, c0, 1 ; Read IFSR
188 mrc p15, 0, R1, c6, c0, 0 ; Read DFAR
191 mrc p15, 0, R1, c5, c0, 0 ; Read DFSR
246 mcr p15, 0, R1, c5, c0, 1 ; Write IFSR
249 mcr p15, 0, R1, c5, c0, 0 ; Write DFSR
DDebugAgentException.S187 mrc p15, 0, R1, c6, c0, 2 @ Read IFAR
190 mrc p15, 0, R1, c5, c0, 1 @ Read IFSR
193 mrc p15, 0, R1, c6, c0, 0 @ Read DFAR
196 mrc p15, 0, R1, c5, c0, 0 @ Read DFSR
251 mcr p15, 0, R1, c5, c0, 1 @ Write IFSR
254 mcr p15, 0, R1, c5, c0, 0 @ Write DFSR
/device/linaro/bootloader/edk2/ArmPkg/Library/ArmExceptionLib/Arm/
DExceptionSupport.asm203 mrc p15, 0, R1, c6, c0, 2 ; Read IFAR
206 mrc p15, 0, R1, c5, c0, 1 ; Read IFSR
209 mrc p15, 0, R1, c6, c0, 0 ; Read DFAR
212 mrc p15, 0, R1, c5, c0, 0 ; Read DFSR
273 mcr p15, 0, R1, c5, c0, 1 ; Write IFSR
276 mcr p15, 0, R1, c5, c0, 0 ; Write DFSR
DExceptionSupport.S209 mrc p15, 0, R1, c6, c0, 2 @ Read IFAR
212 mrc p15, 0, R1, c5, c0, 1 @ Read IFSR
215 mrc p15, 0, R1, c6, c0, 0 @ Read DFAR
218 mrc p15, 0, R1, c5, c0, 0 @ Read DFSR
279 mcr p15, 0, R1, c5, c0, 1 @ Write IFSR
282 mcr p15, 0, R1, c5, c0, 0 @ Write DFSR
/device/linaro/bootloader/edk2/EmbeddedPkg/Library/GdbDebugAgent/Arm/
DExceptionSupport.ARMv6.asm180 mrc p15, 0, R1, c6, c0, 2 ; Read IFAR
183 mrc p15, 0, R1, c5, c0, 1 ; Read IFSR
186 mrc p15, 0, R1, c6, c0, 0 ; Read DFAR
189 mrc p15, 0, R1, c5, c0, 0 ; Read DFSR

123