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/device/linaro/bootloader/edk2/MdePkg/Library/BaseLib/X64/
DRdRand.asm18 ; Generates random number through CPU RdRand instruction under 64-bit platform.
27 ; Generates a 16 bit random number through RDRAND instruction.
46 ; Generates a 32 bit random number through RDRAND instruction.
65 ; Generates a 64 bit random number through one RDRAND instruction.
DRdRand.nasm18 ; Generates random number through CPU RdRand instruction under 64-bit platform.
28 ; Generates a 16 bit random number through RDRAND instruction.
47 ; Generates a 32 bit random number through RDRAND instruction.
66 ; Generates a 64 bit random number through one RDRAND instruction.
DDisableCache.S19 # WBINVD instruction.
DEnableCache.S18 # Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear
/device/linaro/bootloader/edk2/MdePkg/Library/BaseLib/Ia32/
DRdRand.asm18 ; Generates random number through CPU RdRand instruction under 32-bit platform.
30 ; Generates a 16 bit random number through RDRAND instruction.
50 ; Generates a 32 bit random number through RDRAND instruction.
70 ; Generates a 64 bit random number through RDRAND instruction.
DRdRand.nasm18 ; Generates random number through CPU RdRand instruction under 32-bit platform.
27 ; Generates a 16 bit random number through RDRAND instruction.
47 ; Generates a 32 bit random number through RDRAND instruction.
67 ; Generates a 64 bit random number through RDRAND instruction.
/device/linaro/bootloader/edk2/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/
DInitializeFpu.S47 # whether the processor supports SSE instruction.
62 # The processor should support SSE instruction and we can use
63 # ldmxcsr instruction
DInitializeFpu.asm53 ; whether the processor supports SSE instruction.
68 ; The processor should support SSE instruction and we can use
69 ; ldmxcsr instruction
DInitializeFpu.nasm51 ; whether the processor supports SSE instruction.
66 ; The processor should support SSE instruction and we can use
67 ; ldmxcsr instruction
/device/linaro/bootloader/edk2/IntelFspPkg/FspSecCore/Ia32/
DInitializeFpu.s50 # whether the processor supports SSE instruction.
65 # The processor should support SSE instruction and we can use
66 # ldmxcsr instruction
DInitializeFpu.asm53 ; whether the processor supports SSE instruction.
68 ; The processor should support SSE instruction and we can use
69 ; ldmxcsr instruction
DSaveRestoreSse.inc19 ; Define SSE instruction set
157 ; whether the processor supports SSE instruction.
180 ; The processor should support SSE instruction and we can use
181 ; ldmxcsr instruction
/device/linaro/bootloader/edk2/IntelFsp2Pkg/FspSecCore/Ia32/
DInitializeFpu.nasm56 ; whether the processor supports SSE instruction.
71 ; The processor should support SSE instruction and we can use
72 ; ldmxcsr instruction
DSaveRestoreSseNasm.inc19 ; Define SSE instruction set
160 ; whether the processor supports SSE instruction.
183 ; The processor should support SSE instruction and we can use
184 ; ldmxcsr instruction
/device/linaro/bootloader/edk2/MdeModulePkg/Universal/EbcDxe/Ia32/
DEbcLowLevel.asm42 ; This function is called to execute an EBC CALLEX instruction
44 ; This instruction requires that we thunk out to external native
105 ; Caller uses above instruction to jump here
174 ; Caller uses above instruction to jump here
DEbcLowLevel.nasm33 ; This function is called to execute an EBC CALLEX instruction
35 ; This instruction requires that we thunk out to external native
97 ; Caller uses above instruction to jump here
166 ; Caller uses above instruction to jump here
/device/linaro/bootloader/edk2/MdePkg/Library/BaseRngLib/
DBaseRngLib.uni4 // BaseRng Library that uses CPU RdRand instruction access to provide
21 …RIPTION #language en-US "BaseRng Library that uses CPU RdRand instruction access to provi…
/device/linaro/bootloader/edk2/MdeModulePkg/Universal/EbcDxe/X64/
DEbcLowLevel.asm34 ; This function is called to execute an EBC CALLEX instruction.
35 ; This instruction requires that we thunk out to external native
DEbcLowLevel.S28 # This function is called to execute an EBC CALLEX instruction.
29 # This instruction requires that we thunk out to external native
DEbcLowLevel.nasm32 ; This function is called to execute an EBC CALLEX instruction.
33 ; This instruction requires that we thunk out to external native
116 ; Caller uses above instruction to jump here
209 ; Caller uses above instruction to jump here
/device/linaro/bootloader/arm-trusted-firmware/docs/plat/
Dnvidia-tegra.rst22 instruction cache, a 64KB 4-way L1 data cache, and a 2MB 16-way L2
29 into the instruction cache, the optimized micro-ops are executed,
30 re-fetched and executed from the instruction cache as long as needed and
34 Instead of using hardware to extract the instruction-level parallelism
/device/linaro/bootloader/edk2/AppPkg/Applications/Python/Python-2.7.2/Objects/
Dlnotab_notes.txt59 number of the current instruction changes. Re-computing the current line for
60 every instruction is a little slow, though, so each time we compute the line
104 If 'a' is false, execution will jump to the POP_BLOCK instruction at offset 17
111 instruction offset matches the offset given for the start of a line by the
/device/linaro/bootloader/edk2/AppPkg/Applications/Python/Python-2.7.10/Objects/
Dlnotab_notes.txt59 number of the current instruction changes. Re-computing the current line for
60 every instruction is a little slow, though, so each time we compute the line
104 If 'a' is false, execution will jump to the POP_BLOCK instruction at offset 17
111 instruction offset matches the offset given for the start of a line by the
/device/linaro/bootloader/edk2/MdePkg/Library/BaseCpuLib/Arm/
DCpuSleep.S7 # MCR p15,0,r0,c7,c0,4 ;Wait for Interrupt instruction
DCpuSleep.asm7 ; MCR p15,0,r0,c7,c0,4 ;Wait for Interrupt instruction

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