1 /*
2  * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef __PMIC_WRAP_INIT_H__
8 #define __PMIC_WRAP_INIT_H__
9 
10 /* external API */
11 int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
12 int32_t pwrap_write(uint32_t adr, uint32_t wdata);
13 
14 static struct mt8173_pmic_wrap_regs *const mt8173_pwrap =
15 	(void *)PMIC_WRAP_BASE;
16 
17 /* timeout setting */
18 enum {
19 	TIMEOUT_RESET       = 50,	/* us */
20 	TIMEOUT_READ        = 50,	/* us */
21 	TIMEOUT_WAIT_IDLE   = 50	/* us */
22 };
23 
24 /* PMIC_WRAP registers */
25 struct mt8173_pmic_wrap_regs {
26 	uint32_t mux_sel;
27 	uint32_t wrap_en;
28 	uint32_t dio_en;
29 	uint32_t sidly;
30 	uint32_t rddmy;
31 	uint32_t si_ck_con;
32 	uint32_t cshext_write;
33 	uint32_t cshext_read;
34 	uint32_t cslext_start;
35 	uint32_t cslext_end;
36 	uint32_t staupd_prd;
37 	uint32_t staupd_grpen;
38 	uint32_t reserved[4];
39 	uint32_t staupd_man_trig;
40 	uint32_t staupd_sta;
41 	uint32_t wrap_sta;
42 	uint32_t harb_init;
43 	uint32_t harb_hprio;
44 	uint32_t hiprio_arb_en;
45 	uint32_t harb_sta0;
46 	uint32_t harb_sta1;
47 	uint32_t man_en;
48 	uint32_t man_cmd;
49 	uint32_t man_rdata;
50 	uint32_t man_vldclr;
51 	uint32_t wacs0_en;
52 	uint32_t init_done0;
53 	uint32_t wacs0_cmd;
54 	uint32_t wacs0_rdata;
55 	uint32_t wacs0_vldclr;
56 	uint32_t wacs1_en;
57 	uint32_t init_done1;
58 	uint32_t wacs1_cmd;
59 	uint32_t wacs1_rdata;
60 	uint32_t wacs1_vldclr;
61 	uint32_t wacs2_en;
62 	uint32_t init_done2;
63 	uint32_t wacs2_cmd;
64 	uint32_t wacs2_rdata;
65 	uint32_t wacs2_vldclr;
66 	uint32_t int_en;
67 	uint32_t int_flg_raw;
68 	uint32_t int_flg;
69 	uint32_t int_clr;
70 	uint32_t sig_adr;
71 	uint32_t sig_mode;
72 	uint32_t sig_value;
73 	uint32_t sig_errval;
74 	uint32_t crc_en;
75 	uint32_t timer_en;
76 	uint32_t timer_sta;
77 	uint32_t wdt_unit;
78 	uint32_t wdt_src_en;
79 	uint32_t wdt_flg;
80 	uint32_t debug_int_sel;
81 	uint32_t dvfs_adr0;
82 	uint32_t dvfs_wdata0;
83 	uint32_t dvfs_adr1;
84 	uint32_t dvfs_wdata1;
85 	uint32_t dvfs_adr2;
86 	uint32_t dvfs_wdata2;
87 	uint32_t dvfs_adr3;
88 	uint32_t dvfs_wdata3;
89 	uint32_t dvfs_adr4;
90 	uint32_t dvfs_wdata4;
91 	uint32_t dvfs_adr5;
92 	uint32_t dvfs_wdata5;
93 	uint32_t dvfs_adr6;
94 	uint32_t dvfs_wdata6;
95 	uint32_t dvfs_adr7;
96 	uint32_t dvfs_wdata7;
97 	uint32_t spminf_sta;
98 	uint32_t cipher_key_sel;
99 	uint32_t cipher_iv_sel;
100 	uint32_t cipher_en;
101 	uint32_t cipher_rdy;
102 	uint32_t cipher_mode;
103 	uint32_t cipher_swrst;
104 	uint32_t dcm_en;
105 	uint32_t dcm_dbc_prd;
106 };
107 
108 enum {
109 	RDATA_WACS_RDATA_SHIFT = 0,
110 	RDATA_WACS_FSM_SHIFT = 16,
111 	RDATA_WACS_REQ_SHIFT = 19,
112 	RDATA_SYNC_IDLE_SHIFT,
113 	RDATA_INIT_DONE_SHIFT,
114 	RDATA_SYS_IDLE_SHIFT,
115 };
116 
117 enum {
118 	RDATA_WACS_RDATA_MASK = 0xffff,
119 	RDATA_WACS_FSM_MASK = 0x7,
120 	RDATA_WACS_REQ_MASK = 0x1,
121 	RDATA_SYNC_IDLE_MASK = 0x1,
122 	RDATA_INIT_DONE_MASK = 0x1,
123 	RDATA_SYS_IDLE_MASK = 0x1,
124 };
125 
126 /* WACS_FSM */
127 enum {
128 	WACS_FSM_IDLE            = 0x00,
129 	WACS_FSM_REQ             = 0x02,
130 	WACS_FSM_WFDLE           = 0x04,
131 	WACS_FSM_WFVLDCLR        = 0x06,
132 	WACS_INIT_DONE           = 0x01,
133 	WACS_SYNC_IDLE           = 0x01,
134 	WACS_SYNC_BUSY           = 0x00
135 };
136 
137 /* error information flag */
138 enum {
139 	E_PWR_INVALID_ARG             = 1,
140 	E_PWR_INVALID_RW              = 2,
141 	E_PWR_INVALID_ADDR            = 3,
142 	E_PWR_INVALID_WDAT            = 4,
143 	E_PWR_INVALID_OP_MANUAL       = 5,
144 	E_PWR_NOT_IDLE_STATE          = 6,
145 	E_PWR_NOT_INIT_DONE           = 7,
146 	E_PWR_NOT_INIT_DONE_READ      = 8,
147 	E_PWR_WAIT_IDLE_TIMEOUT       = 9,
148 	E_PWR_WAIT_IDLE_TIMEOUT_READ  = 10,
149 	E_PWR_INIT_SIDLY_FAIL         = 11,
150 	E_PWR_RESET_TIMEOUT           = 12,
151 	E_PWR_TIMEOUT                 = 13,
152 	E_PWR_INIT_RESET_SPI          = 20,
153 	E_PWR_INIT_SIDLY              = 21,
154 	E_PWR_INIT_REG_CLOCK          = 22,
155 	E_PWR_INIT_ENABLE_PMIC        = 23,
156 	E_PWR_INIT_DIO                = 24,
157 	E_PWR_INIT_CIPHER             = 25,
158 	E_PWR_INIT_WRITE_TEST         = 26,
159 	E_PWR_INIT_ENABLE_CRC         = 27,
160 	E_PWR_INIT_ENABLE_DEWRAP      = 28,
161 	E_PWR_INIT_ENABLE_EVENT       = 29,
162 	E_PWR_READ_TEST_FAIL          = 30,
163 	E_PWR_WRITE_TEST_FAIL         = 31,
164 	E_PWR_SWITCH_DIO              = 32
165 };
166 
167 #endif /* __PMIC_WRAP_INIT_H__ */
168