1 /* 2 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above 10 * copyright notice, this list of conditions and the following 11 * disclaimer in the documentation and/or other materials provided 12 * with the distribution. 13 * * Neither the name of The Linux Foundation nor the names of its 14 * contributors may be used to endorse or promote products derived 15 * from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 24 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 26 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 27 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #ifndef __DRM_INTERFACE_H__ 31 #define __DRM_INTERFACE_H__ 32 33 #include <map> 34 #include <string> 35 #include <utility> 36 #include <vector> 37 #include <bitset> 38 39 #include "xf86drm.h" 40 #include "xf86drmMode.h" 41 #include <drm/msm_drm.h> 42 #include <drm/msm_drm_pp.h> 43 44 namespace sde_drm { 45 46 typedef std::map<std::pair<uint32_t, uint64_t>, float> CompRatioMap; 47 48 /* 49 * Drm Atomic Operation Codes 50 */ 51 enum struct DRMOps { 52 /* 53 * Op: Sets plane source crop 54 * Arg: uint32_t - Plane ID 55 * DRMRect - Source Rectangle 56 */ 57 PLANE_SET_SRC_RECT, 58 /* 59 * Op: Sets plane destination rect 60 * Arg: uint32_t - Plane ID 61 * DRMRect - Dst Rectangle 62 */ 63 PLANE_SET_DST_RECT, 64 /* 65 * Op: Sets plane exclusion rect 66 * Arg: uint32_t - Plane ID 67 * drm_clip_rect - Exclusion Rectangle 68 */ 69 PLANE_SET_EXCL_RECT, 70 /* 71 * Op: Sets plane zorder 72 * Arg: uint32_t - Plane ID 73 * uint32_t - zorder 74 */ 75 PLANE_SET_ZORDER, 76 /* 77 * Op: Sets plane rotation flags 78 * Arg: uint32_t - Plane ID 79 * uint32_t - bit mask of rotation flags (See drm_mode.h for enums) 80 */ 81 PLANE_SET_ROTATION, 82 /* 83 * Op: Sets plane alpha 84 * Arg: uint32_t - Plane ID 85 * uint32_t - alpha value 86 */ 87 PLANE_SET_ALPHA, 88 /* 89 * Op: Sets the blend type 90 * Arg: uint32_t - Plane ID 91 * uint32_t - blend type (see DRMBlendType) 92 */ 93 PLANE_SET_BLEND_TYPE, 94 /* 95 * Op: Sets horizontal decimation 96 * Arg: uint32_t - Plane ID 97 * uint32_t - decimation factor 98 */ 99 PLANE_SET_H_DECIMATION, 100 /* 101 * Op: Sets vertical decimation 102 * Arg: uint32_t - Plane ID 103 * uint32_t - decimation factor 104 */ 105 PLANE_SET_V_DECIMATION, 106 /* 107 * Op: Sets source config flags 108 * Arg: uint32_t - Plane ID 109 * uint32_t - flags to enable or disable a specific op. E.g. deinterlacing 110 */ 111 PLANE_SET_SRC_CONFIG, 112 /* 113 * Op: Sets frame buffer ID for plane. Set together with CRTC. 114 * Arg: uint32_t - Plane ID 115 * uint32_t - Framebuffer ID 116 */ 117 PLANE_SET_FB_ID, 118 /* 119 * Op: Sets the crtc for this plane. Set together with FB_ID. 120 * Arg: uint32_t - Plane ID 121 * uint32_t - CRTC ID 122 */ 123 PLANE_SET_CRTC, 124 /* 125 * Op: Sets acquire fence for this plane's buffer. Set together with FB_ID, CRTC. 126 * Arg: uint32_t - Plane ID 127 * uint32_t - Input fence 128 */ 129 PLANE_SET_INPUT_FENCE, 130 /* 131 * Op: Sets scaler config on this plane. 132 * Arg: uint32_t - Plane ID 133 * uint64_t - Address of the scaler config object (version based) 134 */ 135 PLANE_SET_SCALER_CONFIG, 136 /* 137 * Op: Sets plane rotation destination rect 138 * Arg: uint32_t - Plane ID 139 * DRMRect - rotator dst Rectangle 140 */ 141 PLANE_SET_ROTATION_DST_RECT, 142 /* 143 * Op: Sets FB Secure mode for this plane. 144 * Arg: uint32_t - Plane ID 145 * uint32_t - Value of the FB Secure mode. 146 */ 147 PLANE_SET_FB_SECURE_MODE, 148 /* 149 * Op: Sets csc config on this plane. 150 * Arg: uint32_t - Plane ID 151 * uint32_t* - pointer to csc type 152 */ 153 PLANE_SET_CSC_CONFIG, 154 /* 155 * Op: Sets multirect mode on this plane. 156 * Arg: uint32_t - Plane ID 157 * uint32_t - multirect mode 158 */ 159 PLANE_SET_MULTIRECT_MODE, 160 /* 161 * Op: Sets rotator output frame buffer ID for plane. 162 * Arg: uint32_t - Plane ID 163 * uint32_t - Framebuffer ID 164 */ 165 PLANE_SET_ROT_FB_ID, 166 /* 167 * Op: Sets inverse pma mode on this plane. 168 * Arg: uint32_t - Plane ID 169 * uint32_t - enable/disable inverse pma. 170 */ 171 PLANE_SET_INVERSE_PMA, 172 /* 173 * Op: Sets csc config on this plane. 174 * Arg: uint32_t - Plane ID 175 * uint64_t - Address of the csc config object(version based) 176 */ 177 PLANE_SET_DGM_CSC_CONFIG, 178 /* 179 * Op: Sets SSPP Feature 180 * Arg: uint32_t - Plane ID 181 * DRMPPFeatureInfo * - PP feature data pointer 182 */ 183 PLANE_SET_POST_PROC, 184 /* 185 * Op: Activate or deactivate a CRTC 186 * Arg: uint32_t - CRTC ID 187 * uint32_t - 1 to enable, 0 to disable 188 */ 189 CRTC_SET_ACTIVE, 190 /* 191 * Op: Sets display mode 192 * Arg: uint32_t - CRTC ID 193 * drmModeModeInfo* - Pointer to display mode 194 */ 195 CRTC_SET_MODE, 196 /* 197 * Op: Sets an offset indicating when a release fence should be signalled. 198 * Arg: uint32_t - offset 199 * 0: non-speculative, default 200 * 1: speculative 201 */ 202 CRTC_SET_OUTPUT_FENCE_OFFSET, 203 /* 204 * Op: Sets overall SDE core clock 205 * Arg: uint32_t - CRTC ID 206 * uint32_t - core_clk 207 */ 208 CRTC_SET_CORE_CLK, 209 /* 210 * Op: Sets MNOC bus average bandwidth 211 * Arg: uint32_t - CRTC ID 212 * uint32_t - core_ab 213 */ 214 CRTC_SET_CORE_AB, 215 /* 216 * Op: Sets MNOC bus instantaneous bandwidth 217 * Arg: uint32_t - CRTC ID 218 * uint32_t - core_ib 219 */ 220 CRTC_SET_CORE_IB, 221 /* 222 * Op: Sets LLCC Bus average bandwidth 223 * Arg: uint32_t - CRTC ID 224 * uint32_t - llcc_ab 225 */ 226 CRTC_SET_LLCC_AB, 227 /* 228 * Op: Sets LLCC Bus instantaneous bandwidth 229 * Arg: uint32_t - CRTC ID 230 * uint32_t - llcc_ib 231 */ 232 CRTC_SET_LLCC_IB, 233 /* 234 * Op: Sets DRAM bus average bandwidth 235 * Arg: uint32_t - CRTC ID 236 * uint32_t - dram_ab 237 */ 238 CRTC_SET_DRAM_AB, 239 /* 240 * Op: Sets DRAM bus instantaneous bandwidth 241 * Arg: uint32_t - CRTC ID 242 * uint32_t - dram_ib 243 */ 244 CRTC_SET_DRAM_IB, 245 /* 246 * Op: Sets Rotator BW for inline rotation 247 * Arg: uint32_t - CRTC ID 248 * uint32_t - rot_bw 249 */ 250 CRTC_SET_ROT_PREFILL_BW, 251 /* 252 * Op: Sets rotator clock for inline rotation 253 * Arg: uint32_t - CRTC ID 254 * uint32_t - rot_clk 255 */ 256 CRTC_SET_ROT_CLK, 257 /* 258 * Op: Sets destination scalar data 259 * Arg: uint32_t - CRTC ID 260 * uint64_t - Pointer to destination scalar data 261 */ 262 CRTC_SET_DEST_SCALER_CONFIG, 263 /* 264 * Op: Returns release fence for this frame. Should be called after Commit() on 265 * DRMAtomicReqInterface. 266 * Arg: uint32_t - CRTC ID 267 * int * - Pointer to an integer that will hold the returned fence 268 */ 269 CRTC_GET_RELEASE_FENCE, 270 /* 271 * Op: Sets PP feature 272 * Arg: uint32_t - CRTC ID 273 * DRMPPFeatureInfo * - PP feature data pointer 274 */ 275 CRTC_SET_POST_PROC, 276 /* 277 * Op: Sets CRTC ROIs. 278 * Arg: uint32_t - CRTC ID 279 * uint32_t - number of ROIs 280 * DRMRect * - Array of CRTC ROIs 281 */ 282 CRTC_SET_ROI, 283 /* 284 * Op: Sets Security level for CRTC. 285 * Arg: uint32_t - CRTC ID 286 * uint32_t - Security level 287 */ 288 CRTC_SET_SECURITY_LEVEL, 289 /* 290 * Op: sets solid fill stages 291 * Arg: uint32_t - CRTC ID 292 * Vector of DRMSolidfillStage 293 */ 294 CRTC_SET_SOLIDFILL_STAGES, 295 /* 296 * Op: Sets idle timeout. 297 * Arg: uint32_t - CRTC ID 298 * uint32_t - idle timeout in ms 299 */ 300 CRTC_SET_IDLE_TIMEOUT, 301 /* 302 * Op: Sets Capture mode for Concurrent Writeback feature. 303 * Arg: uint32_t - CRTC ID 304 * uint32_t - Capture mode 305 */ 306 CRTC_SET_CAPTURE_MODE, 307 /* 308 * Op: Sets Idle PC state for CRTC. 309 * Arg: uint32_t - CRTC ID 310 * uint32_t - idle pc state 311 */ 312 CRTC_SET_IDLE_PC_STATE, 313 /* 314 * Op: Returns retire fence for this commit. Should be called after Commit() on 315 * DRMAtomicReqInterface. 316 * Arg: uint32_t - Connector ID 317 * int * - Pointer to an integer that will hold the returned fence 318 */ 319 CONNECTOR_GET_RETIRE_FENCE, 320 /* 321 * Op: Sets writeback connector destination rect 322 * Arg: uint32_t - Connector ID 323 * DRMRect - Dst Rectangle 324 */ 325 CONNECTOR_SET_OUTPUT_RECT, 326 /* 327 * Op: Sets frame buffer ID for writeback connector. 328 * Arg: uint32_t - Connector ID 329 * uint32_t - Framebuffer ID 330 */ 331 CONNECTOR_SET_OUTPUT_FB_ID, 332 /* 333 * Op: Sets power mode for connector. 334 * Arg: uint32_t - Connector ID 335 * uint32_t - Power Mode 336 */ 337 CONNECTOR_SET_POWER_MODE, 338 /* 339 * Op: Sets panel ROIs. 340 * Arg: uint32_t - Connector ID 341 * uint32_t - number of ROIs 342 * DRMRect * - Array of Connector ROIs 343 */ 344 CONNECTOR_SET_ROI, 345 /* 346 * Op: Sets the connector to autorefresh mode. 347 * Arg: uint32_t - Connector ID 348 * uint32_t - Enable-1, Disable-0 349 */ 350 CONNECTOR_SET_AUTOREFRESH, 351 /* 352 * Op: Set FB secure mode for Writeback connector. 353 * Arg: uint32_t - Connector ID 354 * uint32_t - FB Secure mode 355 */ 356 CONNECTOR_SET_FB_SECURE_MODE, 357 /* 358 * Op: Sets a crtc id to this connector 359 * Arg: uint32_t - Connector ID 360 * uint32_t - CRTC ID 361 */ 362 CONNECTOR_SET_CRTC, 363 /* 364 * Op: Sets PP feature 365 * Arg: uint32_t - Connector ID 366 * DRMPPFeatureInfo * - PP feature data pointer 367 */ 368 CONNECTOR_SET_POST_PROC, 369 /* 370 * Op: Sets connector hdr metadata 371 * Arg: uint32_t - Connector ID 372 * drm_msm_ext_hdr_metadata - hdr_metadata 373 */ 374 CONNECTOR_SET_HDR_METADATA, 375 /* 376 * Op: Cache Dpps features. 377 * Arg: uint32_t - Object ID 378 uint32_t - Feature ID 379 * uint64_t - Pointer to feature config data 380 */ 381 DPPS_CACHE_FEATURE, 382 /* 383 * Op: Commit Dpps features. 384 * Arg: drmModeAtomicReq - Atomic request 385 */ 386 DPPS_COMMIT_FEATURE, 387 /* 388 * Op: Sets qsync mode on connector 389 * Arg: uint32_t - Connector ID 390 * uint32_t - qsync mode 391 */ 392 CONNECTOR_SET_QSYNC_MODE, 393 /* 394 * Op: Sets topology control on this connector 395 * Arg: uint32_t - Connector ID 396 * uint32_t - Topology control bit-mask 397 */ 398 CONNECTOR_SET_TOPOLOGY_CONTROL, 399 }; 400 401 enum struct DRMRotation { 402 FLIP_H = 0x1, 403 FLIP_V = 0x2, 404 ROT_180 = FLIP_H | FLIP_V, 405 ROT_90 = 0x4, 406 }; 407 408 enum struct DRMPowerMode { 409 ON, 410 DOZE, 411 DOZE_SUSPEND, 412 OFF, 413 }; 414 415 enum struct DRMBlendType { 416 UNDEFINED = 0, 417 OPAQUE = 1, 418 PREMULTIPLIED = 2, 419 COVERAGE = 3, 420 }; 421 422 enum struct DRMSrcConfig { 423 DEINTERLACE = 0, 424 }; 425 426 enum struct DRMIdlePCState { 427 NONE, 428 ENABLE, 429 DISABLE, 430 }; 431 432 433 /* Display type to identify a suitable connector */ 434 enum struct DRMDisplayType { 435 PERIPHERAL, 436 TV, 437 VIRTUAL, 438 }; 439 440 struct DRMRect { 441 uint32_t left; // Left-most pixel coordinate. 442 uint32_t top; // Top-most pixel coordinate. 443 uint32_t right; // Right-most pixel coordinate. 444 uint32_t bottom; // Bottom-most pixel coordinate. 445 }; 446 447 //------------------------------------------------------------------------ 448 // DRM Info Query Types 449 //------------------------------------------------------------------------ 450 451 enum struct QSEEDVersion { 452 V1, 453 V2, 454 V3, 455 V3LITE, 456 }; 457 458 /* QSEED3 Step version */ 459 enum struct QSEEDStepVersion { 460 V2, 461 V3, 462 V4, 463 V3LITE_V4, 464 V3LITE_V5, 465 }; 466 467 enum struct SmartDMARevision { 468 V1, 469 V2, 470 V2p5 471 }; 472 473 /* Inline Rotation version */ 474 enum struct InlineRotationVersion { 475 UNKNOWN, 476 V1, 477 V1p1, // Rotator FB ID needs to be set 478 }; 479 480 /* Per CRTC Resource Info*/ 481 struct DRMCrtcInfo { 482 bool has_src_split; 483 bool has_hdr; 484 uint32_t max_blend_stages; 485 uint32_t max_solidfill_stages; 486 QSEEDVersion qseed_version; 487 SmartDMARevision smart_dma_rev; 488 float ib_fudge_factor; 489 float clk_fudge_factor; 490 uint32_t dest_scale_prefill_lines; 491 uint32_t undersized_prefill_lines; 492 uint32_t macrotile_prefill_lines; 493 uint32_t nv12_prefill_lines; 494 uint32_t linear_prefill_lines; 495 uint32_t downscale_prefill_lines; 496 uint32_t extra_prefill_lines; 497 uint32_t amortized_threshold; 498 uint64_t max_bandwidth_low; 499 uint64_t max_bandwidth_high; 500 uint32_t max_sde_clk; 501 CompRatioMap comp_ratio_rt_map; 502 CompRatioMap comp_ratio_nrt_map; 503 uint32_t hw_version; 504 uint32_t dest_scaler_count = 0; 505 uint32_t max_dest_scaler_input_width = 0; 506 uint32_t max_dest_scaler_output_width = 0; 507 uint32_t max_dest_scale_up = 1; 508 uint32_t min_prefill_lines = 0; 509 int secure_disp_blend_stage = -1; 510 bool concurrent_writeback = false; 511 uint32_t num_mnocports = 0; 512 uint32_t mnoc_bus_width = 0; 513 bool use_baselayer_for_stage = false; 514 uint32_t vig_limit_index = 0; 515 uint32_t dma_limit_index = 0; 516 uint32_t scaling_limit_index = 0; 517 uint32_t rotation_limit_index = 0; 518 uint32_t line_width_constraints_count = 0; 519 std::vector< std::pair <uint32_t, uint32_t> > line_width_limits; 520 float vbif_cmd_ff = 0.0f; 521 }; 522 523 enum struct DRMPlaneType { 524 // Has CSC and scaling capability 525 VIG = 0, 526 // Has scaling capability but no CSC 527 RGB, 528 // No scaling support 529 DMA, 530 // Supports a small dimension and doesn't use a CRTC stage 531 CURSOR, 532 MAX, 533 }; 534 535 enum struct DRMTonemapLutType { 536 DMA_1D_GC, 537 DMA_1D_IGC, 538 VIG_1D_IGC, 539 VIG_3D_GAMUT, 540 }; 541 542 struct DRMPlaneTypeInfo { 543 DRMPlaneType type; 544 uint32_t master_plane_id; 545 // FourCC format enum and modifier 546 std::vector<std::pair<uint32_t, uint64_t>> formats_supported; 547 uint32_t max_linewidth; 548 uint32_t max_scaler_linewidth; 549 uint32_t max_upscale; 550 uint32_t max_downscale; 551 uint32_t max_horizontal_deci; 552 uint32_t max_vertical_deci; 553 uint64_t max_pipe_bandwidth; 554 uint32_t cache_size; // cache size in bytes for inline rotation support. 555 bool has_excl_rect = false; 556 QSEEDStepVersion qseed3_version; 557 bool multirect_prop_present = false; 558 InlineRotationVersion inrot_version; // inline rotation version 559 bool inverse_pma = false; 560 uint32_t dgm_csc_version = 0; // csc used with DMA 561 std::map<DRMTonemapLutType, uint32_t> tonemap_lut_version_map = {}; 562 bool block_sec_ui = false; 563 // Allow all planes to be usable on all displays by default 564 std::bitset<32> hw_block_mask = std::bitset<32>().set(); 565 }; 566 567 // All DRM Planes as map<Plane_id , plane_type_info> listed from highest to lowest priority 568 typedef std::vector<std::pair<uint32_t, DRMPlaneTypeInfo>> DRMPlanesInfo; 569 570 enum struct DRMTopology { 571 UNKNOWN, // To be compat with driver defs in sde_rm.h 572 SINGLE_LM, 573 SINGLE_LM_DSC, 574 DUAL_LM, 575 DUAL_LM_DSC, 576 DUAL_LM_MERGE, 577 DUAL_LM_MERGE_DSC, 578 DUAL_LM_DSCMERGE, 579 PPSPLIT, 580 }; 581 582 enum struct DRMPanelMode { 583 VIDEO, 584 COMMAND, 585 }; 586 587 /* Per mode info */ 588 struct DRMModeInfo { 589 drmModeModeInfo mode; 590 DRMTopology topology; 591 // Valid only if mode is command 592 int num_roi; 593 int xstart; 594 int ystart; 595 int walign; 596 int halign; 597 int wmin; 598 int hmin; 599 bool roi_merge; 600 uint64_t bit_clk_rate; 601 uint32_t transfer_time_us; 602 }; 603 604 /* Per Connector Info*/ 605 struct DRMConnectorInfo { 606 uint32_t mmWidth; 607 uint32_t mmHeight; 608 uint32_t type; 609 uint32_t type_id; 610 std::vector<DRMModeInfo> modes; 611 std::string panel_name; 612 DRMPanelMode panel_mode; 613 bool is_primary; 614 // Valid only if DRMPanelMode is VIDEO 615 bool dynamic_fps; 616 // FourCC format enum and modifier 617 std::vector<std::pair<uint32_t, uint64_t>> formats_supported; 618 // Valid only if type is DRM_MODE_CONNECTOR_VIRTUAL 619 uint32_t max_linewidth; 620 DRMRotation panel_orientation; 621 drm_panel_hdr_properties panel_hdr_prop; 622 drm_msm_ext_hdr_properties ext_hdr_prop; 623 bool qsync_support; 624 // Connection status of this connector 625 bool is_connected; 626 bool is_wb_ubwc_supported; 627 uint32_t topology_control; 628 bool dyn_bitclk_support; 629 std::vector<uint8_t> edid; 630 }; 631 632 // All DRM Connectors as map<Connector_id , connector_info> 633 typedef std::map<uint32_t, DRMConnectorInfo> DRMConnectorsInfo; 634 635 /* Per Encoder Info */ 636 struct DRMEncoderInfo { 637 uint32_t type; 638 }; 639 640 // All DRM Encoders as map<Encoder_id , encoder_info> 641 typedef std::map<uint32_t, DRMEncoderInfo> DRMEncodersInfo; 642 643 /* Identifier token for a display */ 644 struct DRMDisplayToken { 645 uint32_t conn_id; 646 uint32_t crtc_id; 647 uint32_t crtc_index; 648 uint32_t encoder_id; 649 uint8_t hw_port; 650 }; 651 652 enum DRMPPFeatureID { 653 kFeaturePcc, 654 kFeatureIgc, 655 kFeaturePgc, 656 kFeatureMixerGc, 657 kFeaturePaV2, 658 kFeatureDither, 659 kFeatureGamut, 660 kFeaturePADither, 661 kFeaturePAHsic, 662 kFeaturePASixZone, 663 kFeaturePAMemColSkin, 664 kFeaturePAMemColSky, 665 kFeaturePAMemColFoliage, 666 kFeaturePAMemColProt, 667 kFeatureDgmIgc, 668 kFeatureDgmGc, 669 kFeatureVigIgc, 670 kFeatureVigGamut, 671 kPPFeaturesMax, 672 }; 673 674 enum DRMPPPropType { 675 kPropEnum, 676 kPropRange, 677 kPropBlob, 678 kPropTypeMax, 679 }; 680 681 struct DRMPPFeatureInfo { 682 DRMPPFeatureID id; 683 DRMPPPropType type; 684 uint32_t version; 685 uint32_t payload_size; 686 void *payload; 687 uint32_t object_type; 688 }; 689 690 enum DRMDPPSFeatureID { 691 // Ad4 properties 692 kFeatureAd4Mode, 693 kFeatureAd4Init, 694 kFeatureAd4Cfg, 695 kFeatureAd4Input, 696 kFeatureAd4Roi, 697 kFeatureAd4Backlight, 698 kFeatureAd4Assertiveness, 699 kFeatureAd4ManualStrength, 700 // ABA properties 701 kFeatureAbaHistCtrl, 702 kFeatureAbaHistIRQ, 703 kFeatureAbaLut, 704 // BL scale properties 705 kFeatureAd4BlScale, 706 kFeatureBacklightScale, 707 // Events 708 kFeaturePowerEvent, 709 kFeatureAbaHistEvent, 710 kFeatureBackLightEvent, 711 kFeatureAdAttBlEvent, 712 // Insert features above 713 kDppsFeaturesMax, 714 }; 715 716 struct DppsFeaturePayload { 717 uint32_t object_type; 718 uint32_t feature_id; 719 uint64_t value; 720 }; 721 722 struct DRMDppsFeatureInfo { 723 DRMDPPSFeatureID id; 724 uint32_t version; 725 }; 726 727 enum AD4Modes { 728 kAd4Off, 729 kAd4AutoStrength, 730 kAd4Calibration, 731 kAd4Manual, 732 kAd4ModeMax, 733 }; 734 735 enum HistModes { 736 kHistDisabled, 737 kHistEnabled, 738 }; 739 740 struct DRMDppsEventInfo { 741 uint32_t object_type; 742 uint32_t event_type; 743 int drm_fd; 744 bool enable; 745 }; 746 747 enum DRMCscType { 748 kCscYuv2Rgb601L, 749 kCscYuv2Rgb601FR, 750 kCscYuv2Rgb709L, 751 kCscYuv2Rgb2020L, 752 kCscYuv2Rgb2020FR, 753 kCscTypeMax, 754 }; 755 756 struct DRMScalerLUTInfo { 757 uint32_t dir_lut_size = 0; 758 uint32_t cir_lut_size = 0; 759 uint32_t sep_lut_size = 0; 760 uint64_t dir_lut = 0; 761 uint64_t cir_lut = 0; 762 uint64_t sep_lut = 0; 763 }; 764 765 enum struct DRMSecureMode { 766 NON_SECURE, 767 SECURE, 768 NON_SECURE_DIR_TRANSLATION, 769 SECURE_DIR_TRANSLATION, 770 }; 771 772 enum struct DRMSecurityLevel { 773 SECURE_NON_SECURE, 774 SECURE_ONLY, 775 }; 776 777 enum struct DRMMultiRectMode { 778 NONE = 0, 779 PARALLEL = 1, 780 SERIAL = 2, 781 }; 782 783 enum struct DRMCWbCaptureMode { 784 MIXER_OUT = 0, 785 DSPP_OUT = 1, 786 }; 787 788 enum struct DRMQsyncMode { 789 NONE = 0, 790 CONTINUOUS, 791 ONESHOT, 792 }; 793 794 enum struct DRMTopologyControl { 795 NONE = 0, 796 RESERVE_LOCK = 1 << 0, 797 RESERVE_CLEAR = 1 << 1, 798 DSPP = 1 << 2, 799 DEST_SCALER = 1 << 3, 800 }; 801 802 struct DRMSolidfillStage { 803 DRMRect bounding_rect {}; 804 bool is_exclusion_rect = false; 805 uint32_t color = 0xff000000; // in 8bit argb 806 uint32_t red = 0; 807 uint32_t blue = 0; 808 uint32_t green = 0; 809 uint32_t alpha = 0xff; 810 uint32_t color_bit_depth = 0; 811 uint32_t z_order = 0; 812 uint32_t plane_alpha = 0xff; 813 }; 814 815 /* DRM Atomic Request Property Set. 816 * 817 * Helper class to create and populate atomic properties of DRM components 818 * when rendered in DRM atomic mode */ 819 class DRMAtomicReqInterface { 820 public: ~DRMAtomicReqInterface()821 virtual ~DRMAtomicReqInterface() {} 822 /* Perform request operation. 823 * 824 * [input]: opcode: operation code from DRMOps list. 825 * obj_id: Relevant crtc, connector, plane id 826 * var_arg: arguments for DRMOps's can differ in number and 827 * data type. Refer above DRMOps to details. 828 * [return]: Error code if the API fails, 0 on success. 829 */ 830 virtual int Perform(DRMOps opcode, uint32_t obj_id, ...) = 0; 831 832 /* 833 * Commit the params set via Perform(). Also resets the properties after commit. Needs to be 834 * called every frame. 835 * [input]: synchronous: Determines if the call should block until a h/w flip 836 * [input]: retain_planes: Retains already staged planes. Useful when not explicitly programming 837 * planes but still need the previously staged ones to not be unstaged 838 * [return]: Error code if the API fails, 0 on success. 839 */ 840 virtual int Commit(bool synchronous, bool retain_planes) = 0; 841 842 /* 843 * Validate the params set via Perform(). 844 * [return]: Error code if the API fails, 0 on success. 845 */ 846 virtual int Validate() = 0; 847 }; 848 849 class DRMManagerInterface; 850 851 /* Populates a singleton instance of DRMManager */ 852 typedef int (*GetDRMManager)(int fd, DRMManagerInterface **intf); 853 854 /* Destroy DRMManager instance */ 855 typedef int (*DestroyDRMManager)(); 856 857 /* 858 * DRM Manager Interface - Any class which plans to implement helper function for vendor 859 * specific DRM driver implementation must implement the below interface routines to work 860 * with SDM. 861 */ 862 863 class DRMManagerInterface { 864 public: ~DRMManagerInterface()865 virtual ~DRMManagerInterface() {} 866 867 /* 868 * Since SDM completely manages the planes. GetPlanesInfo will provide all 869 * the plane information. 870 * [output]: DRMPlanesInfo: Resource Info for planes. 871 */ 872 virtual void GetPlanesInfo(DRMPlanesInfo *info) = 0; 873 874 /* 875 * Will provide all the information of a selected crtc. 876 * [input]: Use crtc id 0 to obtain system wide info 877 * [output]: DRMCrtcInfo: Resource Info for the given CRTC id. 878 * [return]: 0 on success, a negative error value otherwise. 879 */ 880 virtual int GetCrtcInfo(uint32_t crtc_id, DRMCrtcInfo *info) = 0; 881 882 /* 883 * Will provide all the information of a selected connector. 884 * [output]: DRMConnectorInfo: Resource Info for the given connector id 885 * [return]: 0 on success, a negative error value otherwise. 886 */ 887 virtual int GetConnectorInfo(uint32_t conn_id, DRMConnectorInfo *info) = 0; 888 889 /* 890 * Provides information on all connectors. 891 * [output]: DRMConnectorsInfo: Resource info for connectors. 892 * [return]: 0 on success, a negative error value otherwise. 893 */ 894 virtual int GetConnectorsInfo(DRMConnectorsInfo *info) = 0; 895 896 /* 897 * Provides information on a selected encoder. 898 * [output]: DRMEncoderInfo: Resource info for the given encoder id. 899 * [return]: 0 on success, a negative error value otherwise. 900 */ 901 virtual int GetEncoderInfo(uint32_t encoder_id, DRMEncoderInfo *info) = 0; 902 903 /* 904 * Provides information on all encoders. 905 * [output]: DRMEncodersInfo: Resource info for encoders. 906 * [return]: 0 on success, a negative error value otherwise. 907 */ 908 virtual int GetEncodersInfo(DRMEncodersInfo *info) = 0; 909 910 /* 911 * Will query post propcessing feature info of a CRTC. 912 * [output]: DRMPPFeatureInfo: CRTC post processing feature info 913 */ 914 virtual void GetCrtcPPInfo(uint32_t crtc_id, DRMPPFeatureInfo *info) = 0; 915 916 /* 917 * Register a logical display to receive a token. 918 * Each display pipeline in DRM is identified by its CRTC and Connector(s). On display connect 919 * (bootup or hotplug), clients should invoke this interface to establish the pipeline for the 920 * display and should get a DisplayToken populated with crtc, encoder and connnector(s) id's. Here 921 * onwards, Client should use this token to represent the display for any Perform operations if 922 * needed. 923 * 924 * [input]: disp_type - Peripheral / TV / Virtual 925 * [output]: DRMDisplayToken - CRTC and Connector IDs for the display. 926 * [return]: 0 on success, a negative error value otherwise. 927 */ 928 virtual int RegisterDisplay(DRMDisplayType disp_type, DRMDisplayToken *tok) = 0; 929 930 /* 931 * Register a logical display to receive a token. 932 * Each display pipeline in DRM is identified by its CRTC and Connector(s). On display connect 933 * (bootup or hotplug), clients should invoke this interface to establish the pipeline for the 934 * display and should get a DisplayToken populated with crtc, encoder and connnector(s) id's. Here 935 * onwards, Client should use this token to represent the display for any Perform operations if 936 * needed. 937 * 938 * [input]: display_id - Connector ID 939 * [output]: DRMDisplayToken - CRTC and Connector id's for the display. 940 * [return]: 0 on success, a negative error value otherwise. 941 */ 942 virtual int RegisterDisplay(int32_t display_id, DRMDisplayToken *token) = 0; 943 944 /* Client should invoke this interface on display disconnect. 945 * [input]: DRMDisplayToken - identifier for the display. 946 */ 947 virtual void UnregisterDisplay(DRMDisplayToken *token) = 0; 948 949 /* 950 * Creates and returns an instance of DRMAtomicReqInterface corresponding to a display token 951 * returned as part of RegisterDisplay API. Needs to be called per display. 952 * [input]: DRMDisplayToken that identifies a display pipeline 953 * [output]: Pointer to an instance of DRMAtomicReqInterface. 954 * [return]: Error code if the API fails, 0 on success. 955 */ 956 virtual int CreateAtomicReq(const DRMDisplayToken &token, DRMAtomicReqInterface **intf) = 0; 957 958 /* 959 * Destroys the instance of DRMAtomicReqInterface 960 * [input]: Pointer to a DRMAtomicReqInterface 961 * [return]: Error code if the API fails, 0 on success. 962 */ 963 virtual int DestroyAtomicReq(DRMAtomicReqInterface *intf) = 0; 964 965 /* 966 * Sets the global scaler LUT 967 * [input]: LUT Info 968 * [return]: Error code if the API fails, 0 on success. 969 */ 970 virtual int SetScalerLUT(const DRMScalerLUTInfo &lut_info) = 0; 971 972 /* 973 * Unsets the global scaler LUT 974 * [input]: None 975 * [return]: Error code if the API fails, 0 on success. 976 */ 977 virtual int UnsetScalerLUT() = 0; 978 979 /* 980 * Get the DPPS feature info 981 * [input]: Dpps feature id, info->id 982 * [output]: Dpps feature version, info->version 983 */ 984 virtual void GetDppsFeatureInfo(DRMDppsFeatureInfo *info) = 0; 985 }; 986 987 } // namespace sde_drm 988 #endif // __DRM_INTERFACE_H__ 989