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Searched defs:instr (Results 1 – 25 of 30) sorted by relevance

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/art/compiler/optimizing/
Dscheduler_arm64.cc26 void SchedulingLatencyVisitorARM64::VisitBinaryOperation(HBinaryOperation* instr) { in VisitBinaryOperation()
82 void SchedulingLatencyVisitorARM64::VisitDiv(HDiv* instr) { in VisitDiv()
135 void SchedulingLatencyVisitorARM64::VisitMul(HMul* instr) { in VisitMul()
196 void SchedulingLatencyVisitorARM64::VisitTypeConversion(HTypeConversion* instr) { in VisitTypeConversion()
205 void SchedulingLatencyVisitorARM64::HandleSimpleArithmeticSIMD(HVecOperation *instr) { in HandleSimpleArithmeticSIMD()
218 void SchedulingLatencyVisitorARM64::VisitVecExtractScalar(HVecExtractScalar* instr) { in VisitVecExtractScalar()
222 void SchedulingLatencyVisitorARM64::VisitVecReduce(HVecReduce* instr) { in VisitVecReduce()
230 void SchedulingLatencyVisitorARM64::VisitVecNeg(HVecNeg* instr) { in VisitVecNeg()
234 void SchedulingLatencyVisitorARM64::VisitVecAbs(HVecAbs* instr) { in VisitVecAbs()
238 void SchedulingLatencyVisitorARM64::VisitVecNot(HVecNot* instr) { in VisitVecNot()
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Dcommon_arm.h87 inline vixl::aarch32::SRegister OutputSRegister(HInstruction* instr) { in OutputSRegister()
93 inline vixl::aarch32::DRegister OutputDRegister(HInstruction* instr) { in OutputDRegister()
99 inline vixl::aarch32::VRegister OutputVRegister(HInstruction* instr) { in OutputVRegister()
108 inline vixl::aarch32::SRegister InputSRegisterAt(HInstruction* instr, int input_index) { in InputSRegisterAt()
114 inline vixl::aarch32::DRegister InputDRegisterAt(HInstruction* instr, int input_index) { in InputDRegisterAt()
120 inline vixl::aarch32::VRegister InputVRegisterAt(HInstruction* instr, int input_index) { in InputVRegisterAt()
130 inline vixl::aarch32::VRegister InputVRegister(HInstruction* instr) { in InputVRegister()
135 inline vixl::aarch32::Register OutputRegister(HInstruction* instr) { in OutputRegister()
139 inline vixl::aarch32::Register InputRegisterAt(HInstruction* instr, int input_index) { in InputRegisterAt()
144 inline vixl::aarch32::Register InputRegister(HInstruction* instr) { in InputRegister()
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Dreference_type_propagation.cc172 HInstruction* instr = iti.Current(); in ValidateTypes() local
386 HInstruction* instr = it.Current(); in VisitBasicBlock() local
547 void ReferenceTypePropagation::RTPVisitor::SetClassAsTypeInfo(HInstruction* instr, in SetClassAsTypeInfo()
584 void ReferenceTypePropagation::RTPVisitor::VisitDeoptimize(HDeoptimize* instr) { in VisitDeoptimize()
588 void ReferenceTypePropagation::RTPVisitor::UpdateReferenceTypeInfo(HInstruction* instr, in UpdateReferenceTypeInfo()
601 void ReferenceTypePropagation::RTPVisitor::VisitNewInstance(HNewInstance* instr) { in VisitNewInstance()
606 void ReferenceTypePropagation::RTPVisitor::VisitNewArray(HNewArray* instr) { in VisitNewArray()
611 void ReferenceTypePropagation::RTPVisitor::VisitParameterValue(HParameterValue* instr) { in VisitParameterValue()
621 void ReferenceTypePropagation::RTPVisitor::UpdateFieldAccessTypeInfo(HInstruction* instr, in UpdateFieldAccessTypeInfo()
638 void ReferenceTypePropagation::RTPVisitor::VisitInstanceFieldGet(HInstanceFieldGet* instr) { in VisitInstanceFieldGet()
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Dcommon_arm64.h81 inline vixl::aarch64::Register OutputRegister(HInstruction* instr) { in OutputRegister()
85 inline vixl::aarch64::Register InputRegisterAt(HInstruction* instr, int input_index) { in InputRegisterAt()
120 inline vixl::aarch64::VRegister OutputFPRegister(HInstruction* instr) { in OutputFPRegister()
124 inline vixl::aarch64::VRegister InputFPRegisterAt(HInstruction* instr, int input_index) { in InputFPRegisterAt()
135 inline vixl::aarch64::CPURegister OutputCPURegister(HInstruction* instr) { in OutputCPURegister()
141 inline vixl::aarch64::CPURegister InputCPURegisterAt(HInstruction* instr, int index) { in InputCPURegisterAt()
147 inline vixl::aarch64::CPURegister InputCPURegisterOrZeroRegAt(HInstruction* instr, in InputCPURegisterOrZeroRegAt()
171 inline vixl::aarch64::Operand InputOperandAt(HInstruction* instr, int input_index) { in InputOperandAt()
241 inline bool Arm64CanEncodeConstantAsImmediate(HConstant* constant, HInstruction* instr) { in Arm64CanEncodeConstantAsImmediate()
301 HInstruction* instr) { in ARM64EncodableConstantOrRegister()
Dscheduler_arm.cc32 void SchedulingLatencyVisitorARM::HandleBinaryOperationLantencies(HBinaryOperation* instr) { in HandleBinaryOperationLantencies()
51 void SchedulingLatencyVisitorARM::VisitAdd(HAdd* instr) { in VisitAdd()
55 void SchedulingLatencyVisitorARM::VisitSub(HSub* instr) { in VisitSub()
59 void SchedulingLatencyVisitorARM::VisitMul(HMul* instr) { in VisitMul()
75 void SchedulingLatencyVisitorARM::HandleBitwiseOperationLantencies(HBinaryOperation* instr) { in HandleBitwiseOperationLantencies()
91 void SchedulingLatencyVisitorARM::VisitAnd(HAnd* instr) { in VisitAnd()
95 void SchedulingLatencyVisitorARM::VisitOr(HOr* instr) { in VisitOr()
99 void SchedulingLatencyVisitorARM::VisitXor(HXor* instr) { in VisitXor()
103 void SchedulingLatencyVisitorARM::VisitRor(HRor* instr) { in VisitRor()
132 void SchedulingLatencyVisitorARM::HandleShiftLatencies(HBinaryOperation* instr) { in HandleShiftLatencies()
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Dselect_generator_test.cc37 void ConstructBasicGraphForSelect(HInstruction* instr) { in ConstructBasicGraphForSelect()
86 HDivZeroCheck* instr = new (GetAllocator()) HDivZeroCheck(parameters_[0], 0); in TEST_F() local
99 HAdd* instr = new (GetAllocator()) HAdd(DataType::Type::kInt32, in TEST_F() local
Dinstruction_simplifier_shared.h41 inline bool HasShifterOperand(HInstruction* instr, InstructionSet isa) { in HasShifterOperand()
Dselect_generator.cc124 HInstruction* instr = true_block->GetFirstInstruction(); in Run() local
129 HInstruction* instr = false_block->GetFirstInstruction(); in Run() local
Dgraph_visualizer.h66 void AddInstructionInterval(HInstruction* instr, size_t start, size_t end) { in AddInstructionInterval()
Dscheduler.h159 SchedulingNode(HInstruction* instr, ScopedArenaAllocator* allocator, bool is_scheduling_barrier) in SchedulingNode()
340 SchedulingNode* GetNode(const HInstruction* instr) const { in GetNode()
Dscheduler_arm64.h163 bool IsSchedulingBarrier(const HInstruction* instr) const override { in IsSchedulingBarrier()
Dsuperblock_cloner.cc42 static bool IsUsedOutsideRegion(const HInstruction* instr, const HBasicBlockSet& bb_set) { in IsUsedOutsideRegion()
534 HInstruction* instr = it.Current(); in CollectLiveOutsAndCheckClonable() local
543 HInstruction* instr = it.Current(); in CollectLiveOutsAndCheckClonable() local
Dgraph_test.cc39 HInstruction* instr = graph->GetIntConstant(4); in CreateIfBlock() local
Dcode_generator_arm64.h780 void MaybeRecordImplicitNullCheck(HInstruction* instr) final { in MaybeRecordImplicitNullCheck()
Dcode_generator_arm_vixl.h750 void MaybeRecordImplicitNullCheck(HInstruction* instr) final { in MaybeRecordImplicitNullCheck()
/art/disassembler/
Ddisassembler_arm64.cc44 void CustomDisassembler::AppendRegisterNameToOutput(const Instruction* instr, in AppendRegisterNameToOutput()
61 void CustomDisassembler::VisitLoadLiteral(const Instruction* instr) { in VisitLoadLiteral()
100 void CustomDisassembler::VisitLoadStoreUnsignedOffset(const Instruction* instr) { in VisitLoadStoreUnsignedOffset()
112 const Instruction* instr = reinterpret_cast<const Instruction*>(begin); in Dump() local
Ddisassembler_x86.cc174 RegFile dst_reg_file, const uint8_t** instr, in DumpAddress()
257 size_t DisassemblerX86::DumpNops(std::ostream& os, const uint8_t* instr) { in DumpNops()
283 size_t DisassemblerX86::DumpInstruction(std::ostream& os, const uint8_t* instr) { in DumpInstruction()
/art/runtime/
Dinstrumentation_test.cc196 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in CheckConfigureStubs() local
223 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in TestEvent() local
355 static bool HasEventListener(const instrumentation::Instrumentation* instr, uint32_t event_type) in HasEventListener()
384 static void ReportEvent(const instrumentation::Instrumentation* instr, in ReportEvent()
477 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in TEST_F() local
628 instrumentation::Instrumentation* instr = runtime->GetInstrumentation(); in TEST_F() local
659 instrumentation::Instrumentation* instr = runtime->GetInstrumentation(); in TEST_F() local
677 instrumentation::Instrumentation* instr = runtime->GetInstrumentation(); in TEST_F() local
725 instrumentation::Instrumentation* instr = runtime->GetInstrumentation(); in TEST_F() local
744 instrumentation::Instrumentation* instr = runtime->GetInstrumentation(); in TEST_F() local
Dcommon_throws.cc463 static bool IsValidImplicitCheck(uintptr_t addr, const Instruction& instr) in IsValidImplicitCheck()
577 const Instruction& instr = accessor.InstructionAt(throw_dex_pc); in ThrowNullPointerExceptionFromDexPC() local
/art/runtime/arch/arm/
Dfault_handler_arm.cc42 uint16_t instr = pc[0] | pc[1] << 8; in GetInstructionSize() local
/art/runtime/interpreter/
Dinterpreter.cc527 static int16_t GetReceiverRegisterForStringInit(const Instruction* instr) { in GetReceiverRegisterForStringInit()
564 const Instruction* instr = &accessor.InstructionAt(dex_pc); in EnterInterpreterFromDeoptimize() local
Dinterpreter_common.h1030 static inline bool IsStringInit(const Instruction* instr, ArtMethod* caller) in IsStringInit()
/art/runtime/entrypoints/quick/
Dquick_trampoline_entrypoints.cc857 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in artQuickProxyInvokeHandler() local
1247 const Instruction& instr = accessor.InstructionAt(dex_pc); in artQuickResolutionTrampoline() local
2423 const Instruction& instr = caller_method->DexInstructions().InstructionAt(dex_pc); in artInvokeInterfaceTrampoline() local
/art/dexdump/
Ddexdump.cc943 const u2 instr = get2LE((const u1*) &accessor.Insns()[insnIdx]); in dumpInstruction() local
/art/dexlayout/
Ddexlayout.cc838 const uint16_t instr = Get2LE((const uint8_t*) &insns[insn_idx]); in DumpInstruction() local

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