Searched refs:BIT_0 (Results 1 – 2 of 2) sorted by relevance
197 #define BIT_0 (1 << 0) macro314 #define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */343 #define PCI_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */376 #define PCI_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */393 #define PCI_CF1_ENA_TXBMU_WR_IDLE BIT_0 /* Enable TX BMU Write IDLE for ASPM */406 #define PEX_DC_EN_COR_ER_RP BIT_0 /* Enable Correctable Error Reporting */804 #define CS_RST_SET BIT_0 /* Set Software Reset */808 #define LED_STAT_OFF BIT_0 /* Status LED Off */818 #define PC_VCC_OFF BIT_0 /* Switch VCC Off */848 #define Y2_IS_CHK_TXA1 BIT_0 /* Descriptor error TXA 1 */[all …]
201 #define BIT_0 0x0001 macro296 #define MDI_SR_EXT_REG_CAPABLE BIT_0 // Extended register capabilities328 #define NWAY_EX_LP_NWAY BIT_0 // link partner is NWAY337 #define PHY_100_ER0_FDX_INDIC BIT_0 // 1 = FDX, 0 = half duplex508 #define CFIG_503_MII BIT_0532 #define CFIG_PROMISCUOUS_MODE BIT_0541 #define CFIG_STRIPPING BIT_0