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Searched refs:Q_CSR (Results 1 – 2 of 2) sorted by relevance

/device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/
Dif_msk.c2158 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); in msk_handle_hwerr()
2163 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); in msk_handle_hwerr()
2575 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); in msk_init()
2576 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); in msk_init()
2577 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); in msk_init()
2598 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); in msk_init()
2599 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); in msk_init()
2600 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); in msk_init()
2615 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_DIS_RX_CHKSUM | BMU_DIS_RX_RSS_HASH); in msk_init()
2773 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_STOP); in mskc_stop_if()
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Dif_mskreg.h564 #define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */ macro