/device/linaro/bootloader/edk2/AppPkg/Applications/Python/Python-2.7.10/Lib/ |
D | linecache.py | 23 cache = {} # The cache variable 29 global cache 30 cache = {} 37 if filename in cache: 38 return cache[filename][2] 52 filenames = cache.keys() 54 if filename in cache: 60 size, mtime, lines, fullname = cache[filename] 66 del cache[filename] 69 del cache[filename] [all …]
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D | runpy.py | 187 cache = sys.path_importer_cache 189 importer = cache[path_name] 194 cache[path_name] = None 210 cache[path_name] = importer
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/device/linaro/bootloader/edk2/AppPkg/Applications/Python/Python-2.7.2/Lib/ |
D | linecache.py | 23 cache = {} # The cache variable 29 global cache 30 cache = {} 37 if filename in cache: 38 return cache[filename][2] 48 filenames = cache.keys() 50 if filename in cache: 56 size, mtime, lines, fullname = cache[filename] 62 del cache[filename] 65 del cache[filename] [all …]
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D | dircache.py | 14 cache = {} variable 18 global cache 19 cache = {} 24 cached_mtime, list = cache[path] 25 del cache[path] 32 cache[path] = mtime, list
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D | shelve.py | 98 self.cache = {} 119 value = self.cache[key] 124 self.cache[key] = value 129 self.cache[key] = value 138 del self.cache[key] 162 if self.writeback and self.cache: 164 for key, entry in self.cache.iteritems(): 167 self.cache = {}
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D | runpy.py | 187 cache = sys.path_importer_cache 189 importer = cache[path_name] 194 cache[path_name] = None 210 cache[path_name] = importer
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/device/linaro/bootloader/arm-trusted-firmware/fdts/ |
D | fvp-base-gicv3-psci-common.dtsi | 102 next-level-cache = <&L2_0>; 111 next-level-cache = <&L2_0>; 120 next-level-cache = <&L2_0>; 129 next-level-cache = <&L2_0>; 138 next-level-cache = <&L2_0>; 147 next-level-cache = <&L2_0>; 156 next-level-cache = <&L2_0>; 165 next-level-cache = <&L2_0>; 169 compatible = "cache";
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D | fvp-base-gicv2-psci.dts | 104 next-level-cache = <&L2_0>; 113 next-level-cache = <&L2_0>; 122 next-level-cache = <&L2_0>; 131 next-level-cache = <&L2_0>; 140 next-level-cache = <&L2_0>; 149 next-level-cache = <&L2_0>; 158 next-level-cache = <&L2_0>; 167 next-level-cache = <&L2_0>; 171 compatible = "cache";
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D | fvp-base-gicv2-psci-aarch32.dts | 104 next-level-cache = <&L2_0>; 113 next-level-cache = <&L2_0>; 122 next-level-cache = <&L2_0>; 131 next-level-cache = <&L2_0>; 140 next-level-cache = <&L2_0>; 149 next-level-cache = <&L2_0>; 158 next-level-cache = <&L2_0>; 167 next-level-cache = <&L2_0>; 171 compatible = "cache";
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D | fvp-base-gicv3-psci-aarch32.dts | 104 next-level-cache = <&L2_0>; 113 next-level-cache = <&L2_0>; 122 next-level-cache = <&L2_0>; 131 next-level-cache = <&L2_0>; 140 next-level-cache = <&L2_0>; 149 next-level-cache = <&L2_0>; 158 next-level-cache = <&L2_0>; 167 next-level-cache = <&L2_0>; 171 compatible = "cache";
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D | fvp-foundation-gicv2-psci.dts | 89 next-level-cache = <&L2_0>; 98 next-level-cache = <&L2_0>; 107 next-level-cache = <&L2_0>; 116 next-level-cache = <&L2_0>; 120 compatible = "cache";
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D | fvp-foundation-gicv3-psci.dts | 89 next-level-cache = <&L2_0>; 98 next-level-cache = <&L2_0>; 107 next-level-cache = <&L2_0>; 116 next-level-cache = <&L2_0>; 120 compatible = "cache";
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/device/linaro/bootloader/edk2/AppPkg/Applications/Python/Python-2.7.2/Objects/ |
D | dictnotes.txt | 63 Data Layout (assuming a 32-bit box with 64 bytes per cache line) 67 and the whole group nearly fills two consecutive cache lines. 69 Larger dicts use the first half of the dictobject structure (one cache 71 for a total of 5.333 entries per cache line). 79 Each additional 8 consumes 1.5 cache lines. Increasing improves 81 the additional cache lines if they are not already in cache. 87 expense of spreading entries over more cache lines and at the 143 retrieved into a cache line. Since accessing items in cache is *much* 144 cheaper than a cache miss, an enticing idea is to probe the adjacent 149 Exploiting cache locality at the expense of additional collisions fails [all …]
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/device/linaro/bootloader/edk2/AppPkg/Applications/Python/Python-2.7.10/Objects/ |
D | dictnotes.txt | 63 Data Layout (assuming a 32-bit box with 64 bytes per cache line) 67 and the whole group nearly fills two consecutive cache lines. 69 Larger dicts use the first half of the dictobject structure (one cache 71 for a total of 5.333 entries per cache line). 79 Each additional 8 consumes 1.5 cache lines. Increasing improves 81 the additional cache lines if they are not already in cache. 87 expense of spreading entries over more cache lines and at the 143 retrieved into a cache line. Since accessing items in cache is *much* 144 cheaper than a cache miss, an enticing idea is to probe the adjacent 149 Exploiting cache locality at the expense of additional collisions fails [all …]
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/device/linaro/bootloader/arm-trusted-firmware/docs/plat/ |
D | nvidia-tegra.rst | 12 Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction 13 and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache. 22 instruction cache, a 64KB 4-way L1 data cache, and a 2MB 16-way L2 23 cache, which services both cores. 28 dedicated, 128MB main-memory-based optimization cache. After being read 29 into the instruction cache, the optimized micro-ops are executed, 30 re-fetched and executed from the instruction cache as long as needed and
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/device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/Arm/ |
D | ArmV7Support.asm | 29 mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line 33 mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line 38 mcr p15, 0, r0, c7, c5, 1 ; invalidate single instruction cache line to PoU 44 mcr p15, 0, r0, c7, c11, 1 ; clean single data cache line to PoU 49 mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line 69 mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache 126 ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit 135 ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit 193 blt Skip ; no cache or only instruction cache at this level 209 orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11 [all …]
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D | ArmV7Support.S | 28 mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line 32 mcr p15, 0, r0, c7, c10, 1 @clean single data cache line 37 mcr p15, 0, r0, c7, c11, 1 @clean single data cache line to PoU 41 mcr p15, 0, r0, c7, c5, 1 @Invalidate single instruction cache line to PoU 46 mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line 65 mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache 192 blt L_Skip @ no cache or only instruction cache at this level 212 orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11 222 add R10, R10, #2 @ increment the cache number
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/device/linaro/poplar/vendor/ |
D | fstab.poplar | 2 /dev/block/platform/soc@f0000000/f9830000.mmc/by-name/cache /cache ext4 nosuid,nodev,n…
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/device/amlogic/yukawa/ |
D | fstab.yukawa | 3 /dev/block/platform/soc/ffe07000.mmc/by-name/cache /cache ext4 discard,noati…
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/device/linaro/hikey/factory-images/ |
D | generate-factory-images-hikey960.sh | 51 cp $ANDROID_BUILD_TOP/out/target/product/hikey960/cache.img tmp/$PRODUCT-$VERSION/ 86 fastboot flash cache cache.img
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/device/generic/goldfish/tools/ |
D | README.md | 37 $OUT/cache.img cache 2
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/device/linaro/bootloader/edk2/MdeModulePkg/Universal/EsrtDxe/ |
D | EsrtDxe.uni | 4 // This driver produces EsrtManagement protocol to manage cache ESRT repository for FMP/Non-FMP ins… 22 … #language en-US "This driver produces EsrtManagement protocol to manage cache ESRT repository fo…
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/device/linaro/hikey/installer/hikey960/ |
D | uefi-flash-all.sh | 49 fastboot flash cache "${ANDROID_PRODUCT_OUT}"/cache.img
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/device/linaro/hikey/hikey960/ |
D | fstab.hikey960 | 7 #/dev/block/platform/soc/ff3b0000.ufs/by-name/cache /cache ext4 discard,noauto_da_allo…
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/device/google/cuttlefish/shared/config/ |
D | fstab.ext4 | 6 /dev/block/by-name/cache /cache ext4 nodev,noatime,nosuid,errors=panic wait
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