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Searched refs:reg (Results 1 – 25 of 129) sorted by relevance

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/art/compiler/utils/x86/
Dmanaged_register_x86_test.cc26 X86ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); in TEST() local
27 EXPECT_TRUE(reg.IsNoRegister()); in TEST()
28 EXPECT_TRUE(!reg.Overlaps(reg)); in TEST()
32 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); in TEST() local
33 EXPECT_TRUE(!reg.IsNoRegister()); in TEST()
34 EXPECT_TRUE(reg.IsCpuRegister()); in TEST()
35 EXPECT_TRUE(!reg.IsXmmRegister()); in TEST()
36 EXPECT_TRUE(!reg.IsX87Register()); in TEST()
37 EXPECT_TRUE(!reg.IsRegisterPair()); in TEST()
38 EXPECT_EQ(EAX, reg.AsCpuRegister()); in TEST()
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Dmanaged_register_x86.cc41 RegisterPair reg; // Used to verify that the enum is in sync. member
53 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { in operator <<() argument
54 if (reg == kNoRegisterPair) { in operator <<()
57 os << X86ManagedRegister::FromRegisterPair(reg); in operator <<()
84 CHECK_EQ(r, kRegisterPairs[r].reg); in AllocIdLow()
93 CHECK_EQ(r, kRegisterPairs[r].reg); in AllocIdHigh()
114 std::ostream& operator<<(std::ostream& os, const X86ManagedRegister& reg) { in operator <<() argument
115 reg.Print(os); in operator <<()
/art/compiler/utils/x86_64/
Dmanaged_register_x86_64_test.cc25 X86_64ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); in TEST() local
26 EXPECT_TRUE(reg.IsNoRegister()); in TEST()
27 EXPECT_TRUE(!reg.Overlaps(reg)); in TEST()
31 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); in TEST() local
32 EXPECT_TRUE(!reg.IsNoRegister()); in TEST()
33 EXPECT_TRUE(reg.IsCpuRegister()); in TEST()
34 EXPECT_TRUE(!reg.IsXmmRegister()); in TEST()
35 EXPECT_TRUE(!reg.IsX87Register()); in TEST()
36 EXPECT_TRUE(!reg.IsRegisterPair()); in TEST()
37 EXPECT_EQ(RAX, reg.AsCpuRegister()); in TEST()
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Dassembler_x86_64.h115 bool IsRegister(CpuRegister reg) const { in IsRegister() argument
117 && ((encoding_[0] & 0x07) == reg.LowBits()) // Register codes match. in IsRegister()
118 && (reg.NeedsRex() == ((rex_ & 1) != 0)); // REX.000B bits match. in IsRegister()
174 explicit Operand(CpuRegister reg) : rex_(0), length_(0), fixup_(nullptr) { SetModRM(3, reg); } in Operand() argument
368 void call(CpuRegister reg);
372 void pushq(CpuRegister reg);
376 void popq(CpuRegister reg);
671 void psllw(XmmRegister reg, const Immediate& shift_count);
672 void pslld(XmmRegister reg, const Immediate& shift_count);
673 void psllq(XmmRegister reg, const Immediate& shift_count);
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/art/compiler/utils/arm/
Dmanaged_register_arm_test.cc25 ArmManagedRegister reg = ManagedRegister::NoRegister().AsArm(); in TEST() local
26 EXPECT_TRUE(reg.IsNoRegister()); in TEST()
27 EXPECT_TRUE(!reg.Overlaps(reg)); in TEST()
31 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); in TEST() local
32 EXPECT_TRUE(!reg.IsNoRegister()); in TEST()
33 EXPECT_TRUE(reg.IsCoreRegister()); in TEST()
34 EXPECT_TRUE(!reg.IsSRegister()); in TEST()
35 EXPECT_TRUE(!reg.IsDRegister()); in TEST()
36 EXPECT_TRUE(!reg.IsRegisterPair()); in TEST()
37 EXPECT_EQ(R0, reg.AsCoreRegister()); in TEST()
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/art/compiler/debug/
Delf_debug_frame_writer.h49 for (int reg = 0; reg < 13; reg++) { in WriteCIE() local
50 if (reg < 4 || reg == 12) { in WriteCIE()
51 opcodes.Undefined(Reg::ArmCore(reg)); in WriteCIE()
53 opcodes.SameValue(Reg::ArmCore(reg)); in WriteCIE()
57 for (int reg = 0; reg < 32; reg++) { in WriteCIE() local
58 if (reg < 16) { in WriteCIE()
59 opcodes.Undefined(Reg::ArmFp(reg)); in WriteCIE()
61 opcodes.SameValue(Reg::ArmFp(reg)); in WriteCIE()
72 for (int reg = 0; reg < 30; reg++) { in WriteCIE() local
73 if (reg < 8 || reg == 16 || reg == 17) { in WriteCIE()
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/art/compiler/utils/arm64/
Dmanaged_register_arm64_test.cc27 Arm64ManagedRegister reg = ManagedRegister::NoRegister().AsArm64(); in TEST() local
28 EXPECT_TRUE(reg.IsNoRegister()); in TEST()
29 EXPECT_TRUE(!reg.Overlaps(reg)); in TEST()
34 Arm64ManagedRegister reg = Arm64ManagedRegister::FromXRegister(X0); in TEST() local
36 EXPECT_TRUE(!reg.IsNoRegister()); in TEST()
37 EXPECT_TRUE(reg.IsXRegister()); in TEST()
38 EXPECT_TRUE(!reg.IsWRegister()); in TEST()
39 EXPECT_TRUE(!reg.IsDRegister()); in TEST()
40 EXPECT_TRUE(!reg.IsSRegister()); in TEST()
41 EXPECT_TRUE(reg.Overlaps(wreg)); in TEST()
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/art/runtime/arch/arm64/
Dcontext_arm64.h53 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR() argument
54 DCHECK_LT(reg, arraysize(gprs_)); in IsAccessibleGPR()
55 return gprs_[reg] != nullptr; in IsAccessibleGPR()
58 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress() argument
59 DCHECK_LT(reg, arraysize(gprs_)); in GetGPRAddress()
60 return gprs_[reg]; in GetGPRAddress()
63 uintptr_t GetGPR(uint32_t reg) override { in GetGPR() argument
65 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfXRegisters)); in GetGPR()
66 DCHECK(IsAccessibleGPR(reg)); in GetGPR()
67 return *gprs_[reg]; in GetGPR()
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/art/runtime/arch/arm/
Dcontext_arm.h53 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR() argument
54 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); in IsAccessibleGPR()
55 return gprs_[reg] != nullptr; in IsAccessibleGPR()
58 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress() argument
59 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); in GetGPRAddress()
60 return gprs_[reg]; in GetGPRAddress()
63 uintptr_t GetGPR(uint32_t reg) override { in GetGPR() argument
64 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); in GetGPR()
65 DCHECK(IsAccessibleGPR(reg)); in GetGPR()
66 return *gprs_[reg]; in GetGPR()
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Djni_frame_arm.h46 size_t reg = 0; // Register for the current argument; if reg >= 4, we shall use stack. in GetCriticalNativeOutArgsSize() local
50 reg += (reg & 1); in GetCriticalNativeOutArgsSize()
52 reg += 1u; in GetCriticalNativeOutArgsSize()
54 reg += 1u; in GetCriticalNativeOutArgsSize()
56 size_t stack_args = std::max(reg, kJniArgumentRegisterCount) - kJniArgumentRegisterCount; in GetCriticalNativeOutArgsSize()
Dcontext_arm.cc61 void ArmContext::SetGPR(uint32_t reg, uintptr_t value) { in SetGPR() argument
62 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); in SetGPR()
63 DCHECK(IsAccessibleGPR(reg)); in SetGPR()
64 DCHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset. in SetGPR()
65 *gprs_[reg] = value; in SetGPR()
68 void ArmContext::SetFPR(uint32_t reg, uintptr_t value) { in SetFPR() argument
69 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfSRegisters)); in SetFPR()
70 DCHECK(IsAccessibleFPR(reg)); in SetFPR()
71 DCHECK_NE(fprs_[reg], &gZero); // Can't overwrite this static value since they are never reset. in SetFPR()
72 *fprs_[reg] = value; in SetFPR()
/art/runtime/arch/x86_64/
Dcontext_x86_64.h56 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR() argument
57 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in IsAccessibleGPR()
58 return gprs_[reg] != nullptr; in IsAccessibleGPR()
61 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress() argument
62 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in GetGPRAddress()
63 return gprs_[reg]; in GetGPRAddress()
66 uintptr_t GetGPR(uint32_t reg) override { in GetGPR() argument
67 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in GetGPR()
68 DCHECK(IsAccessibleGPR(reg)); in GetGPR()
69 return *gprs_[reg]; in GetGPR()
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Dasm_support_x86_64.S75 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size argument
76 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
77 #define CFI_RESTORE(reg) .cfi_restore reg argument
78 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size argument
84 #define CFI_RESTORE_STATE_AND_DEF_CFA(reg,off) .cfi_restore_state .cfi_def_cfa reg,off argument
91 #define CFI_DEF_CFA(reg,size) argument
92 #define CFI_DEF_CFA_REGISTER(reg) argument
93 #define CFI_RESTORE(reg) argument
94 #define CFI_REL_OFFSET(reg,size) argument
147 MACRO1(PUSH, reg)
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Dcontext_x86_64.cc89 void X86_64Context::SetGPR(uint32_t reg, uintptr_t value) { in SetGPR() argument
90 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in SetGPR()
91 DCHECK(IsAccessibleGPR(reg)); in SetGPR()
92 CHECK_NE(gprs_[reg], &gZero); in SetGPR()
93 *gprs_[reg] = value; in SetGPR()
96 void X86_64Context::SetFPR(uint32_t reg, uintptr_t value) { in SetFPR() argument
97 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfFloatRegisters)); in SetFPR()
98 DCHECK(IsAccessibleFPR(reg)); in SetFPR()
99 CHECK_NE(fprs_[reg], reinterpret_cast<const uint64_t*>(&gZero)); in SetFPR()
100 *fprs_[reg] = value; in SetFPR()
/art/runtime/arch/x86/
Dcontext_x86.h52 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR() argument
53 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in IsAccessibleGPR()
54 return gprs_[reg] != nullptr; in IsAccessibleGPR()
57 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress() argument
58 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in GetGPRAddress()
59 return gprs_[reg]; in GetGPRAddress()
62 uintptr_t GetGPR(uint32_t reg) override { in GetGPR() argument
63 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in GetGPR()
64 DCHECK(IsAccessibleGPR(reg)); in GetGPR()
65 return *gprs_[reg]; in GetGPR()
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Dasm_support_x86.S76 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size argument
77 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
78 #define CFI_RESTORE(reg) .cfi_restore reg argument
79 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size argument
85 #define CFI_RESTORE_STATE_AND_DEF_CFA(reg,off) .cfi_restore_state .cfi_def_cfa reg,off argument
92 #define CFI_DEF_CFA(reg,size) argument
93 #define CFI_DEF_CFA_REGISTER(reg) argument
94 #define CFI_RESTORE(reg) argument
95 #define CFI_REL_OFFSET(reg,size) argument
97 #define CFI_RESTORE_STATE_AND_DEF_CFA(reg,off) argument
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Dcontext_x86.cc77 void X86Context::SetGPR(uint32_t reg, uintptr_t value) { in SetGPR() argument
78 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in SetGPR()
79 DCHECK(IsAccessibleGPR(reg)); in SetGPR()
80 CHECK_NE(gprs_[reg], &gZero); in SetGPR()
81 *gprs_[reg] = value; in SetGPR()
84 void X86Context::SetFPR(uint32_t reg, uintptr_t value) { in SetFPR() argument
85 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfFloatRegisters)); in SetFPR()
86 DCHECK(IsAccessibleFPR(reg)); in SetFPR()
87 CHECK_NE(fprs_[reg], reinterpret_cast<const uint32_t*>(&gZero)); in SetFPR()
88 *fprs_[reg] = value; in SetFPR()
/art/runtime/
Ddex_register_location.cc25 std::ostream& operator<<(std::ostream& stream, const DexRegisterLocation& reg) { in operator <<() argument
27 switch (reg.GetKind()) { in operator <<()
33 return stream << "sp+" << reg.GetValue(); in operator <<()
35 return stream << "r" << reg.GetValue(); in operator <<()
37 return stream << "r" << reg.GetValue() << "/hi"; in operator <<()
39 return stream << "f" << reg.GetValue(); in operator <<()
41 return stream << "f" << reg.GetValue() << "/hi"; in operator <<()
43 return stream << "#" << reg.GetValue(); in operator <<()
45 return stream << "DexRegisterLocation(" << static_cast<uint32_t>(reg.GetKind()) in operator <<()
46 << "," << reg.GetValue() << ")"; in operator <<()
/art/test/404-optimizing-allocator/src/
DMain.java23 expectEquals(4, $opt$reg$TestLostCopy()); in main()
24 expectEquals(-10, $opt$reg$TestTwoLive()); in main()
25 expectEquals(-20, $opt$reg$TestThreeLive()); in main()
26 expectEquals(5, $opt$reg$TestFourLive()); in main()
27 expectEquals(10, $opt$reg$TestMultipleLive()); in main()
28 expectEquals(1, $opt$reg$TestWithBreakAndContinue()); in main()
29 expectEquals(-15, $opt$reg$testSpillInIf(5, 6, 7)); in main()
30 expectEquals(-567, $opt$reg$TestAgressiveLive1(1, 2, 3, 4, 5, 6, 7)); in main()
31 expectEquals(-77, $opt$reg$TestAgressiveLive2(1, 2, 3, 4, 5, 6, 7)); in main()
34 public static int $opt$reg$TestLostCopy() { in $opt$reg$TestLostCopy()
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/art/libelffile/dwarf/
Ddebug_frame_opcode_writer.h73 void ALWAYS_INLINE RelOffset(Reg reg, int offset) { in RelOffset() argument
74 Offset(reg, offset - current_cfa_offset_); in RelOffset()
119 void ALWAYS_INLINE Offset(Reg reg, int offset) { in Offset() argument
124 if (0 <= reg.num() && reg.num() <= 0x3F) { in Offset()
125 this->PushUint8(DW_CFA_offset | reg.num()); in Offset()
129 this->PushUleb128(reg.num()); in Offset()
135 this->PushUleb128(reg.num()); in Offset()
141 void ALWAYS_INLINE Restore(Reg reg) { in Restore() argument
144 if (0 <= reg.num() && reg.num() <= 0x3F) { in Restore()
145 this->PushUint8(DW_CFA_restore | reg.num()); in Restore()
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/art/runtime/arch/
Dcontext.h64 virtual bool IsAccessibleGPR(uint32_t reg) = 0;
67 virtual uintptr_t* GetGPRAddress(uint32_t reg) = 0;
71 virtual uintptr_t GetGPR(uint32_t reg) = 0;
75 virtual void SetGPR(uint32_t reg, uintptr_t value) = 0;
78 virtual bool IsAccessibleFPR(uint32_t reg) = 0;
82 virtual uintptr_t GetFPR(uint32_t reg) = 0;
86 virtual void SetFPR(uint32_t reg, uintptr_t value) = 0;
/art/runtime/interpreter/mterp/arm/
Dmain.S199 .macro FETCH_ADVANCE_INST_RB reg argument
200 ldrh rINST, [rPC, \reg]!
209 .macro FETCH reg, count
210 ldrh \reg, [rPC, #((\count)*2)]
213 .macro FETCH_S reg, count
214 ldrsh \reg, [rPC, #((\count)*2)]
222 .macro FETCH_B reg, count, byte
223 ldrb \reg, [rPC, #((\count)*2+(\byte))]
229 .macro GET_INST_OPCODE reg argument
230 and \reg, rINST, #255
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/art/runtime/interpreter/mterp/arm64/
Dmain.S193 .macro FETCH_ADVANCE_INST_RB reg argument
194 add xPC, xPC, \reg, sxtw
204 .macro FETCH reg, count
205 ldrh \reg, [xPC, #((\count)*2)]
208 .macro FETCH_S reg, count
209 ldrsh \reg, [xPC, #((\count)*2)]
217 .macro FETCH_B reg, count, byte
218 ldrb \reg, [xPC, #((\count)*2+(\byte))]
224 .macro GET_INST_OPCODE reg argument
225 and \reg, xINST, #255
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/art/libdexfile/dex/
Ddex_file-inl.h249 for (uint16_t reg = 0; reg < registers_size; reg++) { in DecodeDebugLocalInfo() local
250 if (local_in_reg[reg].is_live_) { in DecodeDebugLocalInfo()
251 local_in_reg[reg].end_address_ = insns_size_in_code_units; in DecodeDebugLocalInfo()
252 new_local_callback(local_in_reg[reg]); in DecodeDebugLocalInfo()
264 uint16_t reg = DecodeUnsignedLeb128(&stream); in DecodeDebugLocalInfo() local
265 if (reg >= registers_size) { in DecodeDebugLocalInfo()
266 LOG(ERROR) << "invalid stream - reg >= reg size (" << reg << " >= " in DecodeDebugLocalInfo()
279 if (local_in_reg[reg].is_live_) { in DecodeDebugLocalInfo()
280 local_in_reg[reg].end_address_ = address; in DecodeDebugLocalInfo()
281 new_local_callback(local_in_reg[reg]); in DecodeDebugLocalInfo()
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/art/compiler/optimizing/
Dregister_allocator_linear_scan.cc37 static int GetHighForLowRegister(int reg) { return reg + 1; } in GetHighForLowRegister() argument
38 static bool IsLowRegister(int reg) { return (reg & 1) == 0; } in IsLowRegister() argument
132 int reg = location.reg(); in BlockRegister() local
135 ? physical_core_register_intervals_[reg] in BlockRegister()
136 : physical_fp_register_intervals_[reg]; in BlockRegister()
141 interval = LiveInterval::MakeFixedInterval(allocator_, reg, type); in BlockRegister()
143 physical_core_register_intervals_[reg] = interval; in BlockRegister()
145 physical_fp_register_intervals_[reg] = interval; in BlockRegister()
148 DCHECK(interval->GetRegister() == reg); in BlockRegister()
349 current->SetRegister(first.reg()); in ProcessInstruction()
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