Searched refs:TEGRA_FLOWCTRL_BASE (Results 1 – 4 of 4) sorted by relevance
24 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU0_CSR),25 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR),26 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 8),27 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 16)31 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU0_EVENTS),32 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS),33 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 8),34 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 16)38 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL),39 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 4),[all …]
44 return mmio_read_32(TEGRA_FLOWCTRL_BASE + off); in tegra_fc_read_32()49 mmio_write_32(TEGRA_FLOWCTRL_BASE + off, val); in tegra_fc_write_32()
49 #define TEGRA_FLOWCTRL_BASE U(0x60007000) macro
74 #define TEGRA_FLOWCTRL_BASE U(0x60007000) macro