1 /*
2  * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef __TEGRA_DEF_H__
8 #define __TEGRA_DEF_H__
9 
10 #include <utils_def.h>
11 
12 /*******************************************************************************
13  * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
14  * call as the `state-id` field in the 'power state' parameter.
15  ******************************************************************************/
16 #define PSTATE_ID_SOC_POWERDN	U(0xD)
17 
18 /*******************************************************************************
19  * Platform power states (used by PSCI framework)
20  *
21  * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
22  * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
23  ******************************************************************************/
24 #define PLAT_MAX_RET_STATE		U(1)
25 #define PLAT_MAX_OFF_STATE		(PSTATE_ID_SOC_POWERDN + U(1))
26 
27 /*******************************************************************************
28  * GIC memory map
29  ******************************************************************************/
30 #define TEGRA_GICD_BASE			U(0x50041000)
31 #define TEGRA_GICC_BASE			U(0x50042000)
32 
33 /*******************************************************************************
34  * Tegra micro-seconds timer constants
35  ******************************************************************************/
36 #define TEGRA_TMRUS_BASE		U(0x60005010)
37 #define TEGRA_TMRUS_SIZE		U(0x1000)
38 
39 /*******************************************************************************
40  * Tegra Clock and Reset Controller constants
41  ******************************************************************************/
42 #define TEGRA_CAR_RESET_BASE		U(0x60006000)
43 #define TEGRA_GPU_RESET_REG_OFFSET	U(0x28C)
44 #define  GPU_RESET_BIT			(U(1) << 24)
45 
46 /*******************************************************************************
47  * Tegra Flow Controller constants
48  ******************************************************************************/
49 #define TEGRA_FLOWCTRL_BASE		U(0x60007000)
50 
51 /*******************************************************************************
52  * Tegra Secure Boot Controller constants
53  ******************************************************************************/
54 #define TEGRA_SB_BASE			U(0x6000C200)
55 
56 /*******************************************************************************
57  * Tegra Exception Vectors constants
58  ******************************************************************************/
59 #define TEGRA_EVP_BASE			U(0x6000F000)
60 
61 /*******************************************************************************
62  * Tegra Miscellaneous register constants
63  ******************************************************************************/
64 #define TEGRA_MISC_BASE			U(0x70000000)
65 #define  HARDWARE_REVISION_OFFSET	U(0x804)
66 
67 /*******************************************************************************
68  * Tegra UART controller base addresses
69  ******************************************************************************/
70 #define TEGRA_UARTA_BASE		U(0x70006000)
71 #define TEGRA_UARTB_BASE		U(0x70006040)
72 #define TEGRA_UARTC_BASE		U(0x70006200)
73 #define TEGRA_UARTD_BASE		U(0x70006300)
74 #define TEGRA_UARTE_BASE		U(0x70006400)
75 
76 /*******************************************************************************
77  * Tegra Power Mgmt Controller constants
78  ******************************************************************************/
79 #define TEGRA_PMC_BASE			U(0x7000E400)
80 
81 /*******************************************************************************
82  * Tegra Memory Controller constants
83  ******************************************************************************/
84 #define TEGRA_MC_BASE			U(0x70019000)
85 
86 /* TZDRAM carveout configuration registers */
87 #define MC_SECURITY_CFG0_0		U(0x70)
88 #define MC_SECURITY_CFG1_0		U(0x74)
89 #define MC_SECURITY_CFG3_0		U(0x9BC)
90 
91 /* Video Memory carveout configuration registers */
92 #define MC_VIDEO_PROTECT_BASE_HI	U(0x978)
93 #define MC_VIDEO_PROTECT_BASE_LO	U(0x648)
94 #define MC_VIDEO_PROTECT_SIZE_MB	U(0x64c)
95 
96 /*******************************************************************************
97  * Tegra TZRAM constants
98  ******************************************************************************/
99 #define TEGRA_TZRAM_BASE		U(0x7C010000)
100 #define TEGRA_TZRAM_SIZE		U(0x10000)
101 
102 #endif /* __TEGRA_DEF_H__ */
103