| /device/linaro/bootloader/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ |
| D | div.asm | 34 RSBS r12, r1, r0, LSR #4
37 RSBS r12, r1, r0, LSR #8
52 ORRS r12, r0, r1
54 RSBS r12, r1, r0, LSR #1
57 RSBS r12, r1, r0, LSR #4
59 RSBS r12, r1, r0, LSR #8
64 RSBS r12, r1, r0, LSR #7
65 SUBCS r0, r0, r1, LSL #7
67 RSBS r12, r1, r0,LSR #6
68 SUBCS r0, r0, r1, LSL #6
[all …]
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| D | div.S | 35 rsbs r12, r1, r0, LSR #4
38 rsbs r12, r1, r0, LSR #8
53 orrs r12, r0, r1
55 rsbs r12, r1, r0, LSR #1
58 rsbs r12, r1, r0, LSR #4
60 rsbs r12, r1, r0, LSR #8
65 rsbs r12, r1, r0, LSR #7
66 subcs r0, r0, r1, LSL #7
68 rsbs r12, r1, r0,LSR #6
69 subcs r0, r0, r1, LSL #6
[all …]
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| D | ctzsi2.S | 18 uxth r3, r0
23 mov r0, r0, lsr ip
24 tst r0, #255
27 mov r0, r0, lsr r3
28 tst r0, #15
32 mov r0, r0, lsr r1
33 tst r0, #3
37 mov r0, r0, lsr r2
38 and r0, r0, #3
40 eor r3, r0, #1
[all …]
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| D | clzsi2.S | 21 movs r3, r0, lsr #16
26 mov r3, r0, lsr r3
28 movne r0, #8
29 moveq r0, #0
32 mov r3, r3, lsr r0
34 movne r0, #4
35 moveq r0, #0
38 mov r3, r3, lsr r0
40 movne r0, #2
41 moveq r0, #0
[all …]
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| /device/linaro/bootloader/arm-trusted-firmware/include/common/aarch32/ |
| D | el3_common_macros.S | 31 ldcopr r0, SCTLR
32 orr r0, r0, r1
33 stcopr r0, SCTLR
40 ldr r0, =\_exception_vectors
41 stcopr r0, VBAR
42 stcopr r0, MVBAR
52 ldr r0, =(SCR_RESET_VAL | SCR_SIF_BIT)
53 stcopr r0, SCR
74 ldcopr r0, NSACR
75 and r0, r0, #NSACR_IMP_DEF_MASK
[all …]
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| /device/linaro/bootloader/arm-trusted-firmware/lib/cpus/aarch32/ |
| D | cortex_a57.S | 19 ldcopr16 r0, r1, CORTEX_A57_ECTLR
20 bic64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT
21 stcopr16 r0, r1, CORTEX_A57_ECTLR
31 ldcopr16 r0, r1, CORTEX_A57_ECTLR
32 orr64_imm r0, r1, CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT
33 bic64_imm r0, r1, (CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK | \
35 stcopr16 r0, r1, CORTEX_A57_ECTLR
46 mov r0, #1
47 stcopr r0, DBGOSDLR
68 cmp r0, #ERRATA_NOT_APPLIES
[all …]
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| D | cpu_helpers.S | 33 cmp r0, #0
38 ldr r1, [r0, #CPU_RESET_FUNC]
63 cmp r0, r2
64 movhi r0, r2
66 push {r0, lr}
70 ldr r0, [r0, #CPU_DATA_CPU_OPS_PTR]
72 cmp r0, #0
79 ldr r1, [r0, r1]
92 mov r6, r0
93 ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR]
[all …]
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| D | cortex_a53.S | 23 ldcopr16 r0, r1, CORTEX_A53_ECTLR
24 bic64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT
25 stcopr16 r0, r1, CORTEX_A53_ECTLR
46 cmp r0, #ERRATA_NOT_APPLIES
48 ldcopr r0, CORTEX_A53_L2ACTLR
49 bic r0, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN
50 orr r0, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH
51 stcopr r0, CORTEX_A53_L2ACTLR
85 cmp r0, #ERRATA_NOT_APPLIES
87 ldcopr16 r0, r1, CORTEX_A53_CPUACTLR
[all …]
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| D | cortex_a72.S | 18 ldcopr16 r0, r1, CORTEX_A72_ECTLR
19 orr64_imm r0, r1, CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT
20 bic64_imm r0, r1, (CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK | \
22 stcopr16 r0, r1, CORTEX_A72_ECTLR
32 ldcopr16 r0, r1, CORTEX_A72_CPUACTLR
33 orr64_imm r0, r1, CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
34 stcopr16 r0, r1, CORTEX_A72_CPUACTLR
46 ldcopr16 r0, r1, CORTEX_A72_ECTLR
47 bic64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT
48 stcopr16 r0, r1, CORTEX_A72_ECTLR
[all …]
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| D | cortex_a32.S | 20 ldcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
21 bic r0, r0, #CORTEX_A32_CPUECTLR_SMPEN_BIT
22 stcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
38 ldcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
39 orr r0, r0, #CORTEX_A32_CPUECTLR_SMPEN_BIT
40 stcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
56 ldcopr r0, SCTLR
57 tst r0, #SCTLR_C_BIT
65 mov r0, #DC_OP_CISW
87 ldcopr r0, SCTLR
[all …]
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| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/ |
| D | CTA15-A7Helper.S | 27 and r1, r0, #ARM_CORE_MASK
28 and r0, r0, #ARM_CLUSTER_MASK
29 add r0, r1, r0, LSR #7
54 and r0, r0, r2
57 cmp r0, r1
58 moveq r0, #1
59 movne r0, #0
69 MOV32 (r0, ARM_CTA15A7_SCC_CFGREG48)
70 ldr r0, [r0]
71 lsr r0, #24
[all …]
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| D | CTA15-A7Helper.asm | 37 and r1, r0, #ARM_CORE_MASK
38 and r0, r0, #ARM_CLUSTER_MASK
39 add r0, r1, r0, LSR #7
65 and r0, r0, r2
68 cmp r0, r1
69 moveq r0, #1
70 movne r0, #0
81 mov32 r0, ARM_CTA15A7_SCC_CFGREG48
82 ldr r0, [r0]
83 lsr r0, #24
[all …]
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| /device/linaro/bootloader/arm-trusted-firmware/bl32/sp_min/aarch32/ |
| D | entrypoint.S | 55 mov r11, r0
79 mov r0, r11
102 mov r0, #0
123 ldr r0, =__DATA_START__
125 sub r1, r1, r0
128 ldr r0, =__BSS_START__
130 sub r1, r1, r0
157 ldr r0, [r2, #SMC_CTX_SCR]
158 and r3, r0, #SCR_NS_BIT /* flags */
161 bic r0, #SCR_NS_BIT
[all …]
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| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/Arm/ |
| D | RTSMHelper.asm | 42 mrc p15, 4, r0, c15, c0, 0
51 mov32 r0, FixedPcdGet32(PcdArmPrimaryCore)
65 mov r0, #ARM_CPU_TYPE_MASK
66 and r1, r1, r0
68 mov r0, #ARM_CPU_TYPE_A15
69 cmp r1, r0
76 ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] ; Read SCU Config reg to get CPU count
80 mrc p15, 1, r0, c9, c0, 2 ; Read C9 register of CP15 to get CPU count
81 lsr r0, #24
85 and r0, r0, #3
[all …]
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| D | RTSMHelper.S | 23 # OUT r0 = SCU Base Address
28 mrc p15, 4, r0, c15, c0, 0
36 MOV32 (r0, FixedPcdGet32 (PcdArmPrimaryCore))
40 # OUT r0 = number of cores present in the system
49 MOV32 (r0, ARM_CPU_TYPE_MASK)
50 and r1, r1, r0
52 MOV32 (r0, ARM_CPU_TYPE_A15)
53 cmp r1, r0
60 ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] @ Read SCU Config reg to get CPU count
64 mrc p15, 1, r0, c9, c0, 2 @ Read C9 register of CP15 to get CPU count
[all …]
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| /device/linaro/bootloader/arm-trusted-firmware/plat/arm/css/common/aarch32/ |
| D | css_helpers.S | 43 ldr r0, =PLAT_ARM_TRUSTED_MAILBOX_BASE
44 ldr r0, [r0]
57 and r1, r0, #MPIDR_CPU_MASK
58 and r0, r0, #MPIDR_CLUSTER_MASK
59 eor r0, r0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order
60 add r0, r1, r0, LSR #6
75 mov r4, r0
79 cmp r0, r1
81 cmp r0, r4
82 moveq r0, #1
[all …]
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| /device/linaro/bootloader/arm-trusted-firmware/drivers/arm/pl011/aarch32/ |
| D | pl011_console.S | 38 cmp r0, #0
47 ldr r3, [r0, #UARTCR]
49 str r3, [r0, #UARTCR]
57 str r1, [r0, #UARTIBRD]
61 str r1, [r0, #UARTFBRD]
63 str r1, [r0, #UARTLCR_H]
66 str r1, [r0, #UARTECR]
69 str r1, [r0, #UARTCR]
71 mov r0, #1
74 mov r0, #0
[all …]
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| /device/linaro/bootloader/arm-trusted-firmware/plat/arm/board/fvp/aarch32/ |
| D | fvp_helpers.S | 65 mov r0, #0
75 ldr r0, =PLAT_ARM_TRUSTED_MAILBOX_BASE
76 ldr r0, [r0]
77 cmp r0, #0
98 ldcopr r0, MPIDR
100 and r0, r1
101 cmp r0, #FVP_PRIMARY_CPU
102 moveq r0, #1
103 movne r0, #0
118 mov r3, r0
[all …]
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| /device/linaro/bootloader/edk2/MdePkg/Library/BaseMemoryLibOptDxe/Arm/ |
| D | ScanMem.S | 68 tst r0, #7 // If it's already aligned skip the next bit
73 ldrb r3, [r0],#1
77 tst r0, #7
90 ldmia r0!, {r5,r6}
109 ldrb r3, [r0], #1
116 movs r0, #0 // not found
120 subs r0, r0, #1 // found
126 subs r0, r0, #3
131 subne.n r0, r0, #4 // or 2nd byte of 1st word
136 adds r0, r0, #1
[all …]
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| /device/linaro/bootloader/arm-trusted-firmware/plat/arm/board/juno/aarch32/ |
| D | juno_helpers.S | 32 cmp r0, #\_revision
44 ldcopr r0, MIDR
45 ubfx r0, r0, #MIDR_PN_SHIFT, #12
47 cmp r0, r1
70 mov r0, #(0xf << EVNTI_SHIFT)
71 orr r0, r0, #EVNTEN_BIT
72 stcopr r0, CNTKCTL
84 mov r0, #((CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
86 stcopr r0, CORTEX_A57_L2CTLR
121 mov r0, #(CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT)
[all …]
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| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmSmcLib/Arm/ |
| D | ArmSmc.S | 21 push {r0}
24 ldr r7, [r0, #28]
25 ldr r6, [r0, #24]
26 ldr r5, [r0, #20]
27 ldr r4, [r0, #16]
28 ldr r3, [r0, #12]
29 ldr r2, [r0, #8]
30 ldr r1, [r0, #4]
31 ldr r0, [r0, #0]
43 str r0, [r8, #0]
[all …]
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| D | ArmSmc.asm | 20 push {r0}
23 ldr r7, [r0, #28]
24 ldr r6, [r0, #24]
25 ldr r5, [r0, #20]
26 ldr r4, [r0, #16]
27 ldr r3, [r0, #12]
28 ldr r2, [r0, #8]
29 ldr r1, [r0, #4]
30 ldr r0, [r0, #0]
42 str r0, [r8, #0]
[all …]
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| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmHvcLib/Arm/ |
| D | ArmHvc.S | 22 push {r0}
25 ldr r7, [r0, #28]
26 ldr r6, [r0, #24]
27 ldr r5, [r0, #20]
28 ldr r4, [r0, #16]
29 ldr r3, [r0, #12]
30 ldr r2, [r0, #8]
31 ldr r1, [r0, #4]
32 ldr r0, [r0, #0]
44 str r0, [r8, #0]
[all …]
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| D | ArmHvc.asm | 21 push {r0}
24 ldr r7, [r0, #28]
25 ldr r6, [r0, #24]
26 ldr r5, [r0, #20]
27 ldr r4, [r0, #16]
28 ldr r3, [r0, #12]
29 ldr r2, [r0, #8]
30 ldr r1, [r0, #4]
31 ldr r0, [r0, #0]
43 str r0, [r8, #0]
[all …]
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| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/Arm/ |
| D | ArmJunoHelper.S | 32 and r1, r0, #ARM_CORE_MASK
33 and r0, r0, #ARM_CLUSTER_MASK
34 add r0, r1, r0, LSR #7
50 LDRL (r0, PrimaryCoreMpid)
68 and r0, r0, r1
72 cmp r0, r1
73 moveq r0, #1
74 movne r0, #0
88 str r0, [r1]
|